Commits · d9708bfeee34bb42195f1223a396d97e8af27ac4 · Projects / FMC DEL 1ns 2cha

22 Aug, 2016 4 commits
- driver updated · d9708bfe
  Jan Pospisil authored Aug 22, 2016
  
  d9708bfe
- added EdgeDetector architecture for both edges detection; added TODO · a84dd5bc
  Jan Pospisil authored Aug 22, 2016
  
  a84dd5bc
- added automatic start-up AD9512 configuration; implemented full clock selection… · 9faab5c0
  Jan Pospisil authored Aug 22, 2016
```
added automatic start-up AD9512 configuration; implemented full clock selection feature; added clock division ratio selection; removed AD9512 SPI slave; fixed FFPG simulation scripts
```
  9faab5c0
- unified "tabs" with the rest of the project (TAB ~ 4 spaces) · 2900dacb
  Jan Pospisil authored Aug 22, 2016
  
  2900dacb
18 Aug, 2016 9 commits
- non-tabifying · 8f0c84ef
  Jan Pospisil authored Aug 18, 2016
  
  8f0c84ef
- added entity for automatic control of AD9512 divider + testbench · 475932c2
  Jan Pospisil authored Aug 18, 2016
  
  475932c2
- changed position of SPI slave initialization to prevent SS_N line glitch · bb9540eb
  Jan Pospisil authored Aug 18, 2016
  
  bb9540eb
- added reset to LOAD_EXT register in WbSlaveWrapper · 544ee006
  Jan Pospisil authored Aug 18, 2016
  
  544ee006
- timing is OK; triggerLatency=0 works · 5e21ea7c
  Jan Pospisil authored Aug 18, 2016
  
  5e21ea7c
- little bit of calibration · 48ce8a91
  Jan Pospisil authored Aug 18, 2016
  
  48ce8a91
- removed one clock domain in top-level, now everything runs on 62.5 MHz; added… · e938e57a
  Jan Pospisil authored Aug 18, 2016
```
removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation
```
  e938e57a
- added default value for lucid beginning of the simulation · 0d512ced
  Jan Pospisil authored Aug 18, 2016
  
  0d512ced
- make OneWire instances better parametrized · 933011a5
  Jan Pospisil authored Aug 18, 2016
  
  933011a5
17 Aug, 2016 5 commits
- fix AD9512 synchronization - now synchronized by Trigger_i · 4a3aa688
  Jan Pospisil authored Aug 17, 2016
  
  4a3aa688
- added memory output registers; improved timing · 7c6f7f70
  Jan Pospisil authored Aug 17, 2016
  
  7c6f7f70
- added bunch-wise configuration possibility · 689cba91
  Jan Pospisil authored Aug 17, 2016
  
  689cba91
- added missing port assignment · 36aac099
  Jan Pospisil authored Aug 17, 2016
  
  36aac099
- added AD9512 synchronization feature (instead of AD9512 reset) · f1b0308f
  Jan Pospisil authored Aug 17, 2016
  
  f1b0308f
16 Aug, 2016 13 commits
- added OneWire function (not working yet); added calculation for pulse configuration · 548e07d3
  Jan Pospisil authored Aug 16, 2016
  
  548e07d3
- TODOs reorganized, added divider generics to OneWire module · 811d92b0
  Jan Pospisil authored Aug 16, 2016
  
  811d92b0
- magical 8 found? · b5dfdd72
  Jan Pospisil authored Aug 16, 2016
  
  b5dfdd72
- added edge detector for trigger input · f34f48b6
  Jan Pospisil authored Aug 16, 2016
  
  f34f48b6
- added readme.txt · a123e07c
  Jan Pospisil authored Aug 16, 2016
  
  a123e07c
- added possibility to write less data to the memories (for shorter SV simulation) · abaf1726
  Jan Pospisil authored Aug 16, 2016
  
  abaf1726
- fixed multi read/write SV reporting issues when accessing slice of the memory · cd3093e2
  Jan Pospisil authored Aug 16, 2016
  
  cd3093e2
- fixed ONE-SHOT issue (when overflow < trigger periodicity) · 8e25fb8d
  Jan Pospisil authored Aug 16, 2016
  
  8e25fb8d
- improved status reporting, added debug register · dbefc491
  Jan Pospisil authored Aug 16, 2016
  
  dbefc491
- fixed WB register "trigger latency" handling · f66860fa
  Jan Pospisil authored Aug 16, 2016
  
  f66860fa
- added debug register; added FSM state to debug register · 9fa27f2e
  Jan Pospisil authored Aug 16, 2016
  
  9fa27f2e
- fixed integer division in DAC functions; added errors report in SV trace debug;… · 33254a7d
  Jan Pospisil authored Aug 16, 2016
```
fixed integer division in DAC functions; added errors report in SV trace debug; added Enable/Disable and Start/Stop functions
```
  33254a7d
- removed old code · 6778f778
  Jan Pospisil authored Aug 16, 2016
  
  6778f778
15 Aug, 2016 4 commits
- added SV debug trace also for MULTI read/write · 2a626e4d
  Jan Pospisil authored Aug 15, 2016
  
  2a626e4d
- added second FMC signals and missing signals to testbench; used debug trace in testbench · 2939b35b
  Jan Pospisil authored Aug 15, 2016
  
  2939b35b
- added debug trace for SV testbench; added WaitForNotBusy function · 6a247f09
  Jan Pospisil authored Aug 15, 2016
  
  6a247f09
- reorganized CDC around pulse generators · 75016619
  Jan Pospisil authored Aug 15, 2016
  
  75016619
12 Aug, 2016 3 commits
- merged CDC for both channels in one entity, common signals have single CDC;… · a44b9d65
  Jan Pospisil authored Aug 12, 2016
```
merged CDC for both channels in one entity, common signals have single CDC; changed LED blinking frequency 5 Hz -> 15 Hz
```
  a44b9d65
- improved timing · 1da240df
  Jan Pospisil authored Aug 12, 2016
  
  1da240df
- improved clock frequencies parametrization; improved reset performance · be85196c
  Jan Pospisil authored Aug 12, 2016
  
  be85196c
11 Aug, 2016 2 commits
- added code for second FMC module · b7248beb
  Jan Pospisil authored Aug 11, 2016
  
  b7248beb
- updated uvm_agents submodule · 45178acf
  Jan Pospisil authored Aug 11, 2016
  
  45178acf