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FMC DEL 1ns 2cha
Commit 6778f778 authored by Jan Pospisil's avatar Jan Pospisil
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removed old code

parent 2a626e4d
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Showing with 3 additions and 69 deletions
hdl/svec/sim/testbench/Testbench.sv
View file @ 6778f778
......@@ -105,7 +105,7 @@ module Testbench;
$display(label);
acc.write(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data);
#1us; // not to issue commands too fast...
#1us; // not to issue commands too fast, to better simulate real behaviour
endtask
task automatic WbRead(uint32_t address, output uint32_t data, input string label = "");
......@@ -116,7 +116,7 @@ module Testbench;
acc.read(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data64[31:0]);
data = data64[31:0];
#1us; // not to issue commands too fast...
#1us; // not to issue commands too fast, to better simulate real behaviour
endtask
task automatic TestSdb;
......@@ -204,74 +204,8 @@ module Testbench;
endtask
task automatic TestReal;
`include "z:/wb_trace.svh"
// // test on CH2
// int i;
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 0);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_SS), 1);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_DIVIDER), 2);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2618);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h3f03);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4505);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4a00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4c00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4e00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5000);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5200);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4b00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4d00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4f00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5100);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5300);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5820);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5a01);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_TRIGGER_THRESHOLD), 'h1999);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4505);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5a01);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_VCXO_VOLTAGE), 'h42b2);
// for (i=0; i<2048*4; i = i+4) begin
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM)+i, 0);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM)+i, 0);
// end
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_OVERFLOW), 'h459c);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_TRIGGER_LATENCY), 'ha);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM), 'h02000020);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM), 'h40000400);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM)+3*4, 'h20000000);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM)+4*4, 'h4);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CH2_DELAY_SET), 'h64);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CH2_DELAY_RESET), 'hc8);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 8);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h48);
// #1ms;
#1ms;
endtask
initial begin
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