timing is OK; triggerLatency=0 works

5e21ea7c · Jan Pospisil · 48ce8a91 · 5e21ea7c
Commit 5e21ea7c authored Aug 18, 2016 by Jan Pospisil
Hide whitespace changes
Inline Side-by-side

Showing with 0 additions and 2 deletions

FfpgCore.vhd hdl/ffpg/rtl/FfpgCore.vhd +0 -2

No files found.
--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
@@ -3,8 +3,6 @@
 --   ? clock selection
 --   ? clock divider
 --   - frequency sense
--   - timing
--   - TEST: TriggerLatency == 0

 library ieee;
 use ieee.std_logic_1164.all;