added entity for automatic control of AD9512 divider + testbench

475932c2 · Jan Pospisil · bb9540eb · 475932c2 · 475932c2
Commit 475932c2 authored Aug 18, 2016 by Jan Pospisil
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Ad9512Control.vhd hdl/ffpg/rtl/Ad9512Control.vhd +363 -0

Ad9512Control_tb.vhd hdl/ffpg/rtl/Ad9512Control_tb.vhd +73 -0

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--- a/hdl/ffpg/rtl/Ad9512Control.vhd
+++ b/hdl/ffpg/rtl/Ad9512Control.vhd
--- a/hdl/ffpg/rtl/Ad9512Control_tb.vhd
+++ b/hdl/ffpg/rtl/Ad9512Control_tb.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all; 
+
+entity Ad9512Control_tb is
+end entity;
+
+architecture testbench of Ad9512Control_tb is
+
+    constant c_ClkFrequency: positive := 100_000_000;
+    constant c_ClkPeriod: time := (1 sec)/real(c_ClkFrequency);
+    
+    signal Clk_ik, Rst_ir, Cfg_i, Busy_o: std_logic := '0';
+    signal ClockSelection_i: std_logic := '0';
+    signal ClockRatioMinus1_ib: unsigned(4 downto 0) := to_unsigned(2-1, 5);
+    signal SpiAd9512Sclk_o, SpiAd9512Mosi_o, SpiAd9512Miso_i, SpiAd9512Cs_on: std_logic := '0';
+    
+    subtype t_Ratio is Integer range 1 to 32;
+
+    procedure f_Tick(ticks: in natural) is begin
+        wait for ticks * c_ClkPeriod;
+    end procedure;
+
+begin
+
+    cDUT: entity work.Ad9512Control(syn)
+        generic map (
+            g_ClkFrequency => c_ClkFrequency
+        )
+        port map (
+            Clk_ik => Clk_ik,
+            Rst_ir => Rst_ir,
+            Cfg_i => Cfg_i,
+            Busy_o => Busy_o,
+            ClockSelection_i => ClockSelection_i,
+            ClockRatioMinus1_ib => ClockRatioMinus1_ib,
+            SpiAd9512Sclk_o => SpiAd9512Sclk_o,
+            SpiAd9512Mosi_o => SpiAd9512Mosi_o,
+            SpiAd9512Miso_i => SpiAd9512Miso_i,
+            SpiAd9512Cs_on => SpiAd9512Cs_on
+        );
+
+    pClk: process is begin
+        Clk_ik <= '0';
+        wait for c_ClkPeriod/2;
+        Clk_ik <= '1';
+        wait for c_ClkPeriod/2;
+    end process;
+    
+    pTest: process is
+        variable Ratio: t_Ratio;
+    begin
+        Rst_ir <= '1';
+        f_Tick(5);
+        Rst_ir <= '0';
+        f_Tick(2300);
+        
+        ClockSelection_i <= '1';
+        Ratio := 23;
+        ClockRatioMinus1_ib <= to_unsigned(Ratio-1, ClockRatioMinus1_ib'length);
+        Cfg_i <= '1';
+        f_Tick(1);
+        ClockSelection_i <= '0';
+        Ratio := 10;
+        ClockRatioMinus1_ib <= to_unsigned(Ratio-1, ClockRatioMinus1_ib'length);
+        Cfg_i <= '0';
+        f_Tick(2300);
+
+        assert false report "NONE. End of simulation." severity failure;
+        wait;
+    end process;
+
+end architecture;
\ No newline at end of file