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F
FMC DEL 1ns 2cha
Commit 1da240df authored by Jan Pospisil's avatar Jan Pospisil
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improved timing

parent be85196c
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Showing with 12 additions and 14 deletions
hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
View file @ 1da240df
......@@ -38,10 +38,10 @@ architecture syn of ClkRfDomain is
signal GenerationEnable: std_logic;
signal OutputEnable: std_logic;
signal AddressEnableCounterReset, AddressEnableCounterOverflow: std_logic;
signal AddressEnableCounterOverflow: std_logic;
signal AddressEnableCounterSetValue: unsigned(TriggerLatency_ib16'range);
signal AddressCounterReset: std_logic;
signal AddressCounterReset, AddressCounterResetOrReset: std_logic;
signal AddressCounterSetValue: unsigned(TriggerLatency_ib16'range);
signal AddressCounterValue: unsigned(SetMemAddress_ob11'range);
......@@ -78,16 +78,17 @@ begin
);
-- for better timing
pAddressEnableCounterReset: process(Clk_ik) is begin
pAddressCounterReset: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
if StreamPosition = (LastStreamPosition - c_MemLatency) - 1 then
AddressEnableCounterReset <= '1';
AddressCounterReset <= '1';
else
AddressEnableCounterReset <= '0';
AddressCounterReset <= '0';
end if;
end if;
end process;
AddressCounterResetOrReset <= AddressCounterReset or Reset_ir;
AddressEnableCounterSetValue <= TriggerLatencyPlusTwo + c_MemLatency;
cAddressEnableCounter: entity work.Counter(syn)
generic map (
......@@ -95,7 +96,7 @@ begin
)
port map (
Clk_ik => Clk_ik,
Reset_ir => AddressEnableCounterReset,
Reset_ir => AddressCounterResetOrReset,
Enable_i => GenerationEnable,
Set_i => Trigger_i,
SetValue_ib => AddressEnableCounterSetValue(4 downto 0),
......@@ -103,9 +104,6 @@ begin
Value_ob => open
);
AddressCounterReset <=
'1' when StreamPosition = (LastStreamPosition - c_MemLatency) else
Reset_ir;
AddressCounterSetValue <= (TriggerLatencyPlusTwo + c_MemLatency);
cAddressCounter: entity work.Counter(syn)
generic map (
......@@ -113,7 +111,7 @@ begin
)
port map (
Clk_ik => Clk_ik,
Reset_ir => AddressCounterReset,
Reset_ir => AddressCounterResetOrReset,
Enable_i => AddressEnableCounterOverflow,
Set_i => Trigger_i,
SetValue_ib => AddressCounterSetValue(15 downto 5),
......
hdl/svec/syn/SvecFfpg.xise
View file @ 1da240df
......@@ -190,7 +190,7 @@
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -226,7 +226,7 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SvecTopFfpg_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SvecTopFfpg_timesim.vhd" xil_pn:valueState="default"/>
......@@ -260,7 +260,7 @@
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
......
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