make OneWire instances better parametrized

933011a5 · Jan Pospisil · 4a3aa688 · 933011a5 · 933011a5 · 933011a5
Commit 933011a5 authored Aug 18, 2016 by Jan Pospisil
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Showing with 6 additions and 4 deletions

FfpgCore.vhd hdl/ffpg/rtl/FfpgCore.vhd +2 -2

SvecTopFfpg.vhd hdl/svec/rtl/SvecTopFfpg.vhd +3 -1

FFPG_driver.py sw/FFPG_driver.py +1 -1

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--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
@@ -214,8 +214,8 @@ begin
            --   CDR_N = 125MHz * 5.0us - 1 = 625 - 1 = 624 = 0x0270
            -- CDR_O = f_CLK * BTP_O - 1
            --   CDR_O = 125MHz * 1.0us - 1 = 125 - 1 = 124 = 0x007C
-            g_CDR_N => 624,
-            g_CDR_O => 124
+            g_CDR_N => (g_ClkFrequency/1e6)*5 - 1,
+            g_CDR_O => (g_ClkFrequency/1e6)*1 - 1
        )
        port map (
            clk_sys_i => Clk_ik,

--- a/hdl/svec/rtl/SvecTopFfpg.vhd
+++ b/hdl/svec/rtl/SvecTopFfpg.vhd
@@ -549,7 +549,9 @@ begin
            g_address_granularity => BYTE,
            g_num_ports => 1,
            g_ow_btp_normal => "5.0",
-            g_ow_btp_overdrive => "1.0"
+            g_ow_btp_overdrive => "1.0",
+            g_CDR_N => (c_ClkSysFrequency/1e6)*5 - 1,
+            g_CDR_O => (c_ClkSysFrequency/1e6)*1 - 1
        )
        port map (
            clk_sys_i => ClkSys_k,

--- a/sw/FFPG_driver.py
+++ b/sw/FFPG_driver.py
@@ -130,7 +130,7 @@ def WaitForNotBusy(register, bit, timeOut, tries, message = '', polarity = 1):

 def SpiInit():
    WbWrite('spi_ss', 1)
-    WbWrite('spi_divider', 2)
+    WbWrite('spi_divider', 2) # up to 150 MHz of FPGA system clock
    WbWrite('spi_ctrl', 0x2618)

 def SpiRead(register):