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F
FMC DEL 1ns 2cha
Commit be85196c authored by Jan Pospisil's avatar Jan Pospisil
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improved clock frequencies parametrization; improved reset performance

parent b7248beb
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Showing with 53 additions and 17 deletions
hdl/ffpg/rtl/FfpgCore.vhd
View file @ be85196c
......@@ -7,6 +7,7 @@
-- - clock dividers synchronization
-- - TEST: TriggerLatency == 0
-- - Trigger_i will be 25 ns long on ClkRf 200 MHz -> edge detector needed!
-- - ClkRfDomain one hierarchy level up (both channels synchronized the same way)
library ieee;
use ieee.std_logic_1164.all;
......@@ -23,7 +24,7 @@ entity FfpgCore is
port (
-- Wishbone connection
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Reset_ira: in std_logic; -- synchronized locally for better timing
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
--- FMC interface
......@@ -90,7 +91,7 @@ architecture syn of FfpgCore is
2 => f_sdb_embed_device(c_FfpgSdbDevice, x"0001_0000")
);
signal Reset_nr: std_logic;
signal Reset_r, Reset_nr: std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal CnxMasterOut: t_wishbone_master_out_array(c_NumWbSlaves-1 downto 0);
......@@ -105,7 +106,14 @@ architecture syn of FfpgCore is
begin
Reset_nr <= not Reset_ir;
cResetSyncerSys: entity work.ResetSyncer(syn)
port map (
Clk_ik => Clk_ik,
Reset_ira => Reset_ira,
Reset_or => Reset_r
);
Reset_nr <= not Reset_r;
----------------------------------
-- WB crossbar
......@@ -145,7 +153,7 @@ begin
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Reset_ir => Reset_r,
Wb_i => CnxMasterOut(c_SlaveFfpgId),
Wb_o => CnxMasterIn(c_SlaveFfpgId),
ClkIn0_ik => ClkIn0_ik,
......@@ -207,7 +215,7 @@ begin
)
port map (
clk_sys_i => Clk_ik,
rst_n_i => Reset_ir,
rst_n_i => Reset_nr,
slave_i => CnxMasterOut(c_SlaveTemperatureId),
slave_o => CnxMasterIn(c_SlaveTemperatureId),
desc_o => open,
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ be85196c
......@@ -240,7 +240,7 @@ begin
cSlowToggle: entity work.SlowToggle(behavioral)
generic map (
g_Width => 4,
g_Ticks => 25_000_000
g_Ticks => g_ClkFrequency/5
)
port map (
Clk_ik => Clk_ik,
......
hdl/svec/rtl/SvecTopFfpg.vhd
View file @ be85196c
......@@ -178,6 +178,34 @@ end entity;
architecture rtl of SvecTopFfpg is
type t_PllSettings is record
InputFrequency: integer; -- in Hz
Divide: integer;
Mult: integer;
RefJitter: real;
end record;
function f_ComputePllDivider(PllSettings: t_PllSettings; OutputFrequency: integer) return integer is
variable VcoFrequency, Result: integer;
begin
assert PllSettings.InputFrequency * PllSettings.Mult rem PllSettings.Divide = 0
report "Cannot set the PLL - VCO frequency is not an integer!"
severity failure;
VcoFrequency := PllSettings.InputFrequency * PllSettings.Mult / PllSettings.Divide;
assert VcoFrequency rem OutputFrequency = 0
report "Cannot set the output frequency to "&integer'image(OutputFrequency)&" Hz - PLL DIVIDE is not an integer!"
severity failure;
Result := VcoFrequency / OutputFrequency;
return Result;
end function;
constant c_PllSettings: t_PllSettings := (
InputFrequency => 20_000_000,
Divide => 1,
Mult => 50,
RefJitter => 0.016
);
constant c_ClkSysFrequency: positive := 125_000_000; -- in Hz
constant c_ClkVmeFrequency: positive := 62_500_000; -- in Hz
......@@ -309,17 +337,17 @@ begin
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
DIVCLK_DIVIDE => c_PllSettings.Divide,
CLKFBOUT_MULT => c_PllSettings.Mult,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkSysFrequency),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16,
CLKOUT1_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkVmeFrequency),
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016
CLKIN_PERIOD => (1.0)/real(c_PllSettings.InputFrequency)*1.0e9, -- in ns
REF_JITTER => c_PllSettings.RefJitter
)
port map (
CLKFBOUT => PllFeedback,
......@@ -645,7 +673,7 @@ begin
cSlowToggle: entity work.SlowToggle(behavioral)
generic map (
g_Width => 1,
g_Ticks => 25_000_000
g_Ticks => c_ClkSysFrequency/5
)
port map (
Clk_ik => ClkSys_k,
......@@ -712,7 +740,7 @@ begin
port map (
-- Wishbone connection
Clk_ik => ClkSys_k,
Reset_ir => Fmc0Reset_r,
Reset_ira => Fmc0Reset_r, -- synchronized locally for better timing
Wb_i => CnxMasterOut(c_SlaveFmc0Id),
Wb_o => CnxMasterIn(c_SlaveFmc0Id),
---- FMC interface
......@@ -834,7 +862,7 @@ begin
port map (
-- Wishbone connection
Clk_ik => ClkSys_k,
Reset_ir => Fmc1Reset_r,
Reset_ira => Fmc1Reset_r, -- synchronized locally for better timing
Wb_i => CnxMasterOut(c_SlaveFmc1Id),
Wb_o => CnxMasterIn(c_SlaveFmc1Id),
---- FMC interface
......
hdl/svec/syn/SvecFfpg.xise
View file @ be85196c
......@@ -130,7 +130,7 @@
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
......@@ -249,7 +249,7 @@
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
......
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