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FMC DEL 1ns 2cha
Commit 2939b35b authored by Jan Pospisil's avatar Jan Pospisil
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added second FMC signals and missing signals to testbench; used debug trace in testbench

parent 6a247f09
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Showing with 189 additions and 68 deletions
hdl/svec/sim/testbench/SvecTopFfpgWrapper.vhd
View file @ 2939b35b
......@@ -110,17 +110,68 @@ entity SvecTopFfpgWrapper is
Fmc0SpiAd9512Mosi_o: out std_logic;
Fmc0SpiAd9512Miso_i: in std_logic;
Fmc0SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc0Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc0Clk2Sel_o: out std_logic;
-- clock output
Fmc0ClkOutP_ok: out std_logic;
Fmc0ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc0Onewire_io: inout std_logic;
-- LEDs
Fmc0Led_ob: out std_logic_vector(4 downto 1)
Fmc0Led_ob: out std_logic_vector(4 downto 1);
------------------------------------------
-- FMC slot 1
------------------------------------------
-- clock
Fmc1ClkIn0P_ik: in std_logic;
Fmc1ClkIn0N_ik: in std_logic;
-- DACs
Fmc1TriggerDac_o_FrameSynchronization_n: out std_logic;
Fmc1TriggerDac_o_SerialClock: out std_logic;
Fmc1TriggerDac_o_SerialData: out std_logic;
Fmc1VcxoDac_o_FrameSynchronization_n: out std_logic;
Fmc1VcxoDac_o_SerialClock: out std_logic;
Fmc1VcxoDac_o_SerialData: out std_logic;
-- output enable
Fmc1Ch1OutputEnable_o: out std_logic;
Fmc1Ch2OutputEnable_o: out std_logic;
-- delay configuration
Fmc1DelayValue_ob: out std_logic_vector(9 downto 0);
Fmc1Ch1SetLe_o: out std_logic;
Fmc1Ch1ResLe_o: out std_logic;
Fmc1Ch2SetLe_o: out std_logic;
Fmc1Ch2ResLe_o: out std_logic;
Fmc1Ch1SetP_o: out std_logic;
Fmc1Ch1SetN_o: out std_logic;
Fmc1Ch1ResP_o: out std_logic;
Fmc1Ch1ResN_o: out std_logic;
Fmc1Ch2SetP_o: out std_logic;
Fmc1Ch2SetN_o: out std_logic;
Fmc1Ch2ResP_o: out std_logic;
Fmc1Ch2ResN_o: out std_logic;
Fmc1TriggerP_i: in std_logic;
Fmc1TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc1SpiAd9512Sclk_o: out std_logic;
Fmc1SpiAd9512Mosi_o: out std_logic;
Fmc1SpiAd9512Miso_i: in std_logic;
Fmc1SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc1Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc1Clk2Sel_o: out std_logic;
-- clock output
Fmc1ClkOutP_ok: out std_logic;
Fmc1ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc1Onewire_io: inout std_logic;
-- LEDs
Fmc1Led_ob: out std_logic_vector(4 downto 1)
);
end entity;
......@@ -130,6 +181,9 @@ architecture wrapper of SvecTopFfpgWrapper is
signal Fmc0TriggerDac_o, Fmc0VcxoDac_o: t_Ad5600Interface;
signal Fmc0DelayValue_ob_unsigned: unsigned(9 downto 0);
signal Fmc1TriggerDac_o, Fmc1VcxoDac_o: t_Ad5600Interface;
signal Fmc1DelayValue_ob_unsigned: unsigned(9 downto 0);
begin
cSvecTopFfpg: entity work.SvecTopFfpg(rtl)
......@@ -211,11 +265,53 @@ begin
Fmc0SpiAd9512Mosi_o => Fmc0SpiAd9512Mosi_o,
Fmc0SpiAd9512Miso_i => Fmc0SpiAd9512Miso_i,
Fmc0SpiAd9512Cs_on => Fmc0SpiAd9512Cs_on,
Fmc0Ad9512Func_o => Fmc0Ad9512Func_o,
Fmc0Clk2Sel_o => Fmc0Clk2Sel_o,
Fmc0ClkOutP_ok => Fmc0ClkOutP_ok,
Fmc0ClkOutN_ok => Fmc0ClkOutN_ok,
Fmc0Onewire_io => Fmc0Onewire_io,
Fmc0Led_ob => Fmc0Led_ob
Fmc0Led_ob => Fmc0Led_ob,
------------------------------------------
-- FMC slot 1
------------------------------------------
Fmc1ClkIn0P_ik => Fmc1ClkIn0P_ik,
Fmc1ClkIn0N_ik => Fmc1ClkIn0N_ik,
Fmc1TriggerDac_o.FrameSynchronization_n => Fmc1TriggerDac_o_FrameSynchronization_n,
Fmc1TriggerDac_o.SerialClock => Fmc1TriggerDac_o_SerialClock,
Fmc1TriggerDac_o.SerialData => Fmc1TriggerDac_o_SerialData,
Fmc1VcxoDac_o.FrameSynchronization_n => Fmc1VcxoDac_o_FrameSynchronization_n,
Fmc1VcxoDac_o.SerialClock => Fmc1VcxoDac_o_SerialClock,
Fmc1VcxoDac_o.SerialData => Fmc1VcxoDac_o_SerialData,
Fmc1Ch1OutputEnable_o => Fmc1Ch1OutputEnable_o,
Fmc1Ch2OutputEnable_o => Fmc1Ch2OutputEnable_o,
Fmc1DelayValue_ob => Fmc1DelayValue_ob_unsigned,
Fmc1Ch1SetLe_o => Fmc1Ch1SetLe_o,
Fmc1Ch1ResLe_o => Fmc1Ch1ResLe_o,
Fmc1Ch2SetLe_o => Fmc1Ch2SetLe_o,
Fmc1Ch2ResLe_o => Fmc1Ch2ResLe_o,
Fmc1Ch1SetP_o => Fmc1Ch1SetP_o,
Fmc1Ch1SetN_o => Fmc1Ch1SetN_o,
Fmc1Ch1ResP_o => Fmc1Ch1ResP_o,
Fmc1Ch1ResN_o => Fmc1Ch1ResN_o,
Fmc1Ch2SetP_o => Fmc1Ch2SetP_o,
Fmc1Ch2SetN_o => Fmc1Ch2SetN_o,
Fmc1Ch2ResP_o => Fmc1Ch2ResP_o,
Fmc1Ch2ResN_o => Fmc1Ch2ResN_o,
Fmc1TriggerP_i => Fmc1TriggerP_i,
Fmc1TriggerN_i => Fmc1TriggerN_i,
Fmc1SpiAd9512Sclk_o => Fmc1SpiAd9512Sclk_o,
Fmc1SpiAd9512Mosi_o => Fmc1SpiAd9512Mosi_o,
Fmc1SpiAd9512Miso_i => Fmc1SpiAd9512Miso_i,
Fmc1SpiAd9512Cs_on => Fmc1SpiAd9512Cs_on,
Fmc1Ad9512Func_o => Fmc1Ad9512Func_o,
Fmc1Clk2Sel_o => Fmc1Clk2Sel_o,
Fmc1ClkOutP_ok => Fmc1ClkOutP_ok,
Fmc1ClkOutN_ok => Fmc1ClkOutN_ok,
Fmc1Onewire_io => Fmc1Onewire_io,
Fmc1Led_ob => Fmc1Led_ob
);
Fmc0DelayValue_ob <= std_logic_vector(Fmc0DelayValue_ob_unsigned);
Fmc1DelayValue_ob <= std_logic_vector(Fmc1DelayValue_ob_unsigned);
end architecture;
\ No newline at end of file
hdl/svec/sim/testbench/Testbench.sv
View file @ 2939b35b
......@@ -37,9 +37,8 @@ module Testbench;
`DECLARE_VME_BUFFERS(VME.slave);
`DECLARE_FMC(0);
`DECLARE_FMC(1);
logic Fmc1Present_in;
logic [1:0] FpLedsLineEnable_ob2;
logic [1:0] FpLedsLine_ob2;
logic [3:0] FpLedsColumn_ob4;
......@@ -52,12 +51,12 @@ module Testbench;
SvecTopFfpgWrapper cDut (
.Clk20_ik(Clk20_ik),
.Reset_inr(Reset_inr),
// Pll20DacDin_o: out std_logic;
// Pll20DacSclk_o: out std_logic;
// Pll20DacSync_on: out std_logic;
// Pll25DacDin_o: out std_logic;
// Pll25DacSclk_o: out std_logic;
// Pll25DacSync_on: out std_logic;
.Pll20DacDin_o(),
.Pll20DacSclk_o(),
.Pll20DacSync_on(),
.Pll25DacDin_o(),
.Pll25DacSclk_o(),
.Pll25DacSync_on(),
.FpLedsLineEnable_ob2(FpLedsLineEnable_ob2),
.FpLedsLine_ob2(FpLedsLine_ob2),
.FpLedsColumn_ob4(FpLedsColumn_ob4),
......@@ -67,20 +66,25 @@ module Testbench;
.CarrierOneWire_io(CarrierOneWire_io),
`WIRE_FMC(0)
`WIRE_FMC(1)
.Fmc1Present_in(Fmc1Present_in),
`WIRE_VME_PINS(8) // slot number in parameter // don't change that magic 8 - it's hardcoded somewhere else
);
assign Fmc0Present_in = 1;
assign Fmc1Present_in = 0;
assign Fmc0ClkIn0P_ik = ClkRf_k;
assign Fmc0ClkIn0N_ik = ~Fmc0ClkIn0P_ik;
assign Fmc0TriggerP_i = Trigger;
assign Fmc0TriggerN_i = ~Fmc0TriggerP_i;
assign Fmc0SpiAd9512Miso_i = Fmc0SpiAd9512Mosi_o; // loopback
assign Fmc1Present_in = 1;
assign Fmc1ClkIn0P_ik = ClkRf_k;
assign Fmc1ClkIn0N_ik = ~Fmc1ClkIn0P_ik;
assign Fmc1TriggerP_i = Trigger;
assign Fmc1TriggerN_i = ~Fmc1TriggerP_i;
assign Fmc1SpiAd9512Miso_i = Fmc1SpiAd9512Mosi_o; // loopback
task automatic init_vme64x_core;
/* map func0 to 0x80000000, A32 */
......@@ -101,6 +105,18 @@ module Testbench;
$display(label);
acc.write(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data);
#1us; // not to issue commands too fast...
endtask
task automatic WbRead(uint32_t address, output uint32_t data, input string label = "");
uint64_t data64;
if (label != "")
$display(label);
acc.read(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data64[31:0]);
data = data64[31:0];
#1us; // not to issue commands too fast...
endtask
task automatic TestSdb;
......@@ -188,71 +204,74 @@ module Testbench;
endtask
task automatic TestReal;
// test on CH2
int i;
`include "z:/wb_trace.svh"
// // test on CH2
// int i;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 0);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 0);
WbWrite(`WB_FFPG_SPI_REG(`SPI_SS), 1);
WbWrite(`WB_FFPG_SPI_REG(`SPI_DIVIDER), 2);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2618);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_SS), 1);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_DIVIDER), 2);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2618);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h3f03);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4505);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4a00);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4c00);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4e00);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5000);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5200);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4b00);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4d00);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4f00);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5100);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5300);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5820);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5a01);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h3f03);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4505);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4a00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4c00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4e00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5000);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5200);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4b00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4d00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4f00);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5100);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5300);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5820);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5a01);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_TRIGGER_THRESHOLD), 'h1999);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4505);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5a01);
WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_TRIGGER_THRESHOLD), 'h1999);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h4505);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_TX_RX_0), 'h5a01);
// WbWrite(`WB_FFPG_SPI_REG(`SPI_CTRL), 'h2718);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_VCXO_VOLTAGE), 'h42b2);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_VCXO_VOLTAGE), 'h42b2);
for (i=0; i<2048*4; i = i+4) begin
WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM)+i, 0);
WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM)+i, 0);
end
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_OVERFLOW), 'h459c);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_TRIGGER_LATENCY), 'ha);
// for (i=0; i<2048*4; i = i+4) begin
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM)+i, 0);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM)+i, 0);
// end
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_OVERFLOW), 'h459c);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_TRIGGER_LATENCY), 'ha);
WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM), 'h02000020);
WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM), 'h40000400);
WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM)+3*4, 'h20000000);
WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM)+4*4, 'h4);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM), 'h02000020);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM), 'h40000400);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_SET_MEM)+3*4, 'h20000000);
// WbWrite(`WB_FFPG_CSR_REG(`BASE_FFPG_CH2_RES_MEM)+4*4, 'h4);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CH2_DELAY_SET), 'h64);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CH2_DELAY_RESET), 'hc8);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CH2_DELAY_SET), 'h64);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CH2_DELAY_RESET), 'hc8);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 8);
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h48);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 8);
// WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h48);
#1ms;
// #1ms;
endtask
initial begin
......
hdl/svec/sim/testbench/fmc.svh
View file @ 2939b35b
......@@ -29,7 +29,10 @@
logic Fmc``__nb``SpiAd9512Mosi_o; \
logic Fmc``__nb``SpiAd9512Miso_i; \
logic Fmc``__nb``SpiAd9512Cs_on; \
logic Fmc``__nb``Ad9512Func_o; \
logic Fmc``__nb``Clk2Sel_o; \
logic Fmc``__nb``ClkOutP_ok; \
logic Fmc``__nb``ClkOutN_ok; \
wire Fmc``__nb``Onewire_io; \
logic [4:1] Fmc``__nb``Led_ob; \
logic Fmc``__nb``Present_in;
......@@ -66,7 +69,10 @@
.Fmc``__nb``SpiAd9512Mosi_o(Fmc``__nb``SpiAd9512Mosi_o), \
.Fmc``__nb``SpiAd9512Miso_i(Fmc``__nb``SpiAd9512Miso_i), \
.Fmc``__nb``SpiAd9512Cs_on(Fmc``__nb``SpiAd9512Cs_on), \
.Fmc``__nb``Ad9512Func_o(Fmc``__nb``Ad9512Func_o), \
.Fmc``__nb``Clk2Sel_o(Fmc``__nb``Clk2Sel_o), \
.Fmc``__nb``ClkOutP_ok(Fmc``__nb``ClkOutP_ok), \
.Fmc``__nb``ClkOutN_ok(Fmc``__nb``ClkOutN_ok), \
.Fmc``__nb``Onewire_io(Fmc``__nb``Onewire_io), \
.Fmc``__nb``Led_ob(Fmc``__nb``Led_ob), \
.Fmc``__nb``Present_in(Fmc``__nb``Present_in),
......
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