Commit 9faab5c0 authored by Jan Pospisil's avatar Jan Pospisil

added automatic start-up AD9512 configuration; implemented full clock selection…

added automatic start-up AD9512 configuration; implemented full clock selection feature; added clock division ratio selection; removed AD9512 SPI slave; fixed FFPG simulation scripts
parent 2900dacb
......@@ -27,7 +27,7 @@ entity Ad9512Control is
);
port (
Clk_ik: in std_logic;
Rst_ir: in std_logic;
Reset_ir: in std_logic;
Cfg_i: in std_logic;
Busy_o: out std_logic;
......@@ -239,7 +239,7 @@ begin
pFsmTransitions: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
if Rst_ir = '1' then
if Reset_ir = '1' then
SeqCurrentState <= c_ResetState;
else
SeqCurrentState <= SeqCurrentState;
......@@ -341,11 +341,11 @@ begin
)
port map (
wb_clk_i => Clk_ik,
wb_rst_i => Rst_ir,
wb_rst_i => Reset_ir,
wb_adr_i => WbAdr_b5,
wb_dat_i => WbDatIn_b32,
wb_dat_o => WbDatOut_b32,
wb_sel_i => (others => '1'),
wb_sel_i => "1111",
wb_we_i => WbWe,
wb_stb_i => WbStb,
wb_cyc_i => WbStb,
......
......@@ -10,7 +10,7 @@ architecture testbench of Ad9512Control_tb is
constant c_ClkFrequency: positive := 100_000_000;
constant c_ClkPeriod: time := (1 sec)/real(c_ClkFrequency);
signal Clk_ik, Rst_ir, Cfg_i, Busy_o: std_logic := '0';
signal Clk_ik, Reset_ir, Cfg_i, Busy_o: std_logic := '0';
signal ClockSelection_i: std_logic := '0';
signal ClockRatioMinus1_ib: unsigned(4 downto 0) := to_unsigned(2-1, 5);
signal SpiAd9512Sclk_o, SpiAd9512Mosi_o, SpiAd9512Miso_i, SpiAd9512Cs_on: std_logic := '0';
......@@ -29,7 +29,7 @@ begin
)
port map (
Clk_ik => Clk_ik,
Rst_ir => Rst_ir,
Reset_ir => Reset_ir,
Cfg_i => Cfg_i,
Busy_o => Busy_o,
ClockSelection_i => ClockSelection_i,
......@@ -50,9 +50,9 @@ begin
pTest: process is
variable Ratio: t_Ratio;
begin
Rst_ir <= '1';
Reset_ir <= '1';
f_Tick(5);
Rst_ir <= '0';
Reset_ir <= '0';
f_Tick(2300);
ClockSelection_i <= '1';
......
library ieee;
use ieee.std_logic_1164.all;
entity ChangeDetector is
port (
Clk_ik: in std_logic;
Signal_ib: in std_logic_vector;
Change_o: out std_logic
);
end entity;
architecture syn of ChangeDetector is
signal History_b: std_logic_vector(Signal_ib'range) := (others => '0');
begin
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History_b <= Signal_ib;
end if;
end process;
pDetection: process (Signal_ib, History_b) is
variable Result: std_logic;
begin
Result := '0';
for i in Signal_ib'range loop
Result := Result or (Signal_ib(i) xor History_b(i));
end loop;
Change_o <= Result;
end process;
end architecture;
-- TODO:
-- - automatic clock infrastructure configuration
-- ? clock selection
-- ? clock divider
-- ! mode_load - not to assert when other control bit is changed
-- - frequency sense
library ieee;
......@@ -67,24 +65,22 @@ architecture syn of FfpgCore is
constant c_NumWbMasters: integer := 1;
-- Number of master port(s) on the wishbone crossbar
constant c_NumWbSlaves: integer := 3;
constant c_NumWbSlaves: integer := 2;
-- Wishbone master(s)
constant c_MasterId: integer := 0;
-- Wishbone slave(s)
constant c_SlaveSpiId: integer := 0;
constant c_SlaveTemperatureId: integer := 1;
constant c_SlaveFfpgId: integer := 2;
constant c_SlaveTemperatureId: integer := 0;
constant c_SlaveFfpgId: integer := 1;
-- sdb header address
constant c_SdbAddress: t_wishbone_address := x"0000_0000";
-- Wishbone crossbar layout
constant c_InterconnectLayout: t_sdb_record_array(c_NumWbSlaves-1 downto 0) := (
0 => f_sdb_embed_device(c_xwb_spi_sdb, x"0000_1000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"0000_1100"),
2 => f_sdb_embed_device(c_FfpgSdbDevice, x"0001_0000")
0 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"0000_1000"),
1 => f_sdb_embed_device(c_FfpgSdbDevice, x"0001_0000")
);
signal Reset_r, Reset_nr: std_logic;
......@@ -169,34 +165,14 @@ begin
Trigger_i => Trigger_i,
Clk2Sel_o => Clk2Sel_o,
Led_ob => Led_ob,
SpiAd9512Cs_on => SpiAd9512Cs_on,
SpiAd9512Sclk_o => SpiAd9512Sclk_o,
SpiAd9512Mosi_o => SpiAd9512Mosi_o,
SpiAd9512Miso_i => SpiAd9512Miso_i,
Ad9512Func_o => Ad9512Func_o,
ClkOut_ok => ClkOut_ok
);
----------------------------------
-- SPI slave for AD9512
----------------------------------
cSpiSlave: entity work.xwb_spi(rtl)
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_divider_len => 16,
g_max_char_len => 128,
g_num_slaves => 1
)
port map (
clk_sys_i => Clk_ik,
rst_n_i => Reset_nr,
slave_i => CnxMasterOut(c_SlaveSpiId),
slave_o => CnxMasterIn(c_SlaveSpiId),
desc_o => open,
pad_cs_o(0) => SpiAd9512Cs_on,
pad_sclk_o => SpiAd9512Sclk_o,
pad_mosi_o => SpiAd9512Mosi_o,
pad_miso_i => SpiAd9512Miso_i
);
----------------------------------
-- 1-wire slave for temperature chip DS18B20
----------------------------------
......
......@@ -40,6 +40,11 @@ entity FfpgSlave is
Clk2Sel_o: out std_logic;
-- LEDs
Led_ob: out std_logic_vector(4 downto 1);
-- AD9512 SPI
SpiAd9512Sclk_o: out std_logic;
SpiAd9512Mosi_o: out std_logic;
SpiAd9512Miso_i: in std_logic;
SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Ad9512Func_o: out std_logic;
-- clock output
......@@ -70,6 +75,8 @@ architecture syn of FfpgSlave is
signal LedSignal_b: std_logic_vector(4 downto 1);
signal Ad9512ClockSelectionChanged: std_logic;
signal Ad9512ClockSelection, Ad9512StartConfig: std_logic;
signal Ad9512SyncePulse: std_logic;
begin
......@@ -195,13 +202,6 @@ begin
Ch2FsmState_o => WbRegsInput.debug_i(5 downto 3)
);
----------------------------------
-- Clock selection (temporary)
----------------------------------
Clk2Sel_o <= WbRegsOutput.control_clock_selection_o(0);
WbRegsInput.control_clock_selection_i <= WbRegsOutput.control_clock_selection_o;
----------------------------------
-- LED outputs
----------------------------------
......@@ -244,9 +244,50 @@ begin
);
----------------------------------
-- Pulse generator board clocks
-- Clock infrastructure
----------------------------------
-- CLOCK_SELECTION [read/write]: Clock source selection
-- 0 (default): external clock used (connector on the front panel)
-- 1: FPGA loop clock used
-- 2: on-board VCXO clock used
Ad9512ClockSelection <=
'0' when WbRegsOutput.control_clock_selection_o = "00" else -- AD9512: CLK1
'1'; -- AD9512: CLK2
Clk2Sel_o <=
'0' when WbRegsOutput.control_clock_selection_o = "01" else -- SY58017: FPGA LOOP
'1'; -- SY58017: VCXO
cAd9512ClockSelectionChange: entity work.ChangeDetector(syn)
port map (
Clk_ik => Clk_ik,
Signal_ib => WbRegsOutput.control_clock_selection_o,
Change_o => Ad9512ClockSelectionChanged
);
Ad9512StartConfig <= WbRegsOutput.clock_ratio_m1_load_o or Ad9512ClockSelectionChanged;
cAd9512Control: entity work.Ad9512Control(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Cfg_i => Ad9512StartConfig,
Busy_o => WbRegsInput.status_clock_infrastructure_busy_i,
ClockSelection_i => Ad9512ClockSelection,
ClockRatioMinus1_ib => WbRegsOutput.clock_ratio_m1_o,
SpiAd9512Sclk_o => SpiAd9512Sclk_o,
SpiAd9512Mosi_o => SpiAd9512Mosi_o,
SpiAd9512Miso_i => SpiAd9512Miso_i,
SpiAd9512Cs_on => SpiAd9512Cs_on
);
cAd9512Syncer: entity work.Ad9512Syncer(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
......@@ -264,11 +305,7 @@ begin
----------------------------------
-- to be used
----------------------------------
-- WbRegsOutput.clock_divider_lo_o
-- WbRegsOutput.clock_divider_hi_o
-- WbRegsOutput.clock_divider_hi_load_o
WbRegsInput.status_clock_infrastructure_busy_i <= 'X';
WbRegsInput.status_clock_selection_busy_i <= 'X';
WbRegsInput.frequency_i <= (others => 'X');
WbRegsInput.debug_i(31 downto 6) <= (others => '0');
......
......@@ -38,11 +38,10 @@ architecture syn of WbSlaveWrapper is
signal WbRegsOutput: t_ffpg_out_registers;
-- registers for LOAD_EXT fields
signal control_clock_selection: std_logic_vector(1 downto 0) := (others => '0');
signal control_ch1_mode: std_logic_vector(1 downto 0) := (others => '0');
signal control_ch2_mode: std_logic_vector(1 downto 0) := (others => '0');
signal vcxo_voltage: unsigned(15 downto 0) := (others => '0');
signal clock_divider_hi: unsigned(3 downto 0) := (others => '0');
signal clock_ratio_m1: unsigned(4 downto 0) := (others => '0');
signal ch1_delay_set: unsigned(9 downto 0) := (others => '0');
signal ch1_delay_reset: unsigned(9 downto 0) := (others => '0');
signal ch2_delay_set: unsigned(9 downto 0) := (others => '0');
......@@ -51,11 +50,10 @@ architecture syn of WbSlaveWrapper is
signal overflow: unsigned(15 downto 0) := (others => '0');
signal trigger_latency: unsigned(15 downto 0) := (others => '0');
-- delayed load signals for LOAD_EXT fields
signal control_clock_selection_load: std_logic := '0';
signal control_ch1_mode_load: std_logic := '0';
signal control_ch2_mode_load: std_logic := '0';
signal vcxo_voltage_load: std_logic := '0';
signal clock_divider_hi_load: std_logic := '0';
signal clock_ratio_m1_load: std_logic := '0';
signal ch1_delay_set_load: std_logic := '0';
signal ch1_delay_reset_load: std_logic := '0';
signal ch2_delay_set_load: std_logic := '0';
......@@ -105,11 +103,10 @@ begin
pLocalRegs: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
control_clock_selection_load <= '0';
control_ch1_mode_load <= '0';
control_ch2_mode_load <= '0';
vcxo_voltage_load <= '0';
clock_divider_hi_load <= '0';
clock_ratio_m1_load <= '0';
ch1_delay_set_load <= '0';
ch1_delay_reset_load <= '0';
ch2_delay_set_load <= '0';
......@@ -118,11 +115,10 @@ begin
overflow_load <= '0';
trigger_latency_load <= '0';
control_clock_selection <= (others => '0');
control_ch1_mode <= (others => '0');
control_ch2_mode <= (others => '0');
vcxo_voltage <= (others => '0');
clock_divider_hi <= (others => '0');
clock_ratio_m1 <= (others => '0');
ch1_delay_set <= (others => '0');
ch1_delay_reset <= (others => '0');
ch2_delay_set <= (others => '0');
......@@ -131,11 +127,10 @@ begin
overflow <= (others => '0');
trigger_latency <= (others => '0');
else
control_clock_selection_load <= '0';
control_ch1_mode_load <= '0';
control_ch2_mode_load <= '0';
vcxo_voltage_load <= '0';
clock_divider_hi_load <= '0';
clock_ratio_m1_load <= '0';
ch1_delay_set_load <= '0';
ch1_delay_reset_load <= '0';
ch2_delay_set_load <= '0';
......@@ -144,10 +139,6 @@ begin
overflow_load <= '0';
trigger_latency_load <= '0';
if WbRegsOutput.control_clock_selection_load_o = '1' then
control_clock_selection <= WbRegsOutput.control_clock_selection_o;
control_clock_selection_load <= '1';
end if;
if WbRegsOutput.control_ch1_mode_load_o = '1' then
control_ch1_mode <= WbRegsOutput.control_ch1_mode_o;
control_ch1_mode_load <= '1';
......@@ -160,9 +151,9 @@ begin
vcxo_voltage <= WbRegsOutput.vcxo_voltage_o;
vcxo_voltage_load <= '1';
end if;
if WbRegsOutput.clock_divider_hi_load_o = '1' then
clock_divider_hi <= WbRegsOutput.clock_divider_hi_o;
clock_divider_hi_load <= '1';
if WbRegsOutput.clock_ratio_m1_load_o = '1' then
clock_ratio_m1 <= WbRegsOutput.clock_ratio_m1_o;
clock_ratio_m1_load <= '1';
end if;
if WbRegsOutput.ch1_delay_set_load_o = '1' then
ch1_delay_set <= WbRegsOutput.ch1_delay_set_o;
......@@ -196,16 +187,15 @@ begin
end if;
end process;
pInputRegisters: process (WbRegs_i, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency) is begin
pInputRegisters: process (WbRegs_i, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_ratio_m1, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency) is begin
-- #!@& ISE doesn't know VHDL 2008 (... process (all) ...)
-- by default, all values are passed
WbRegsInput <= WbRegs_i;
-- LOAD_EXT inputs are overwritten by local registers
WbRegsInput.control_clock_selection_i <= control_clock_selection;
WbRegsInput.control_ch1_mode_i <= control_ch1_mode;
WbRegsInput.control_ch2_mode_i <= control_ch2_mode;
WbRegsInput.vcxo_voltage_i <= vcxo_voltage;
WbRegsInput.clock_divider_hi_i <= clock_divider_hi;
WbRegsInput.clock_ratio_m1_i <= clock_ratio_m1;
WbRegsInput.ch1_delay_set_i <= ch1_delay_set;
WbRegsInput.ch1_delay_reset_i <= ch1_delay_reset;
WbRegsInput.ch2_delay_set_i <= ch2_delay_set;
......@@ -215,16 +205,15 @@ begin
WbRegsInput.trigger_latency_i <= trigger_latency;
end process;
pOutputRegisters: process (WbRegsOutput, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency, control_clock_selection_load, control_ch1_mode_load, control_ch2_mode_load, vcxo_voltage_load, clock_divider_hi_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, trigger_latency_load) is begin
pOutputRegisters: process (WbRegsOutput, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_ratio_m1, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency, control_ch1_mode_load, control_ch2_mode_load, vcxo_voltage_load, clock_ratio_m1_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, trigger_latency_load) is begin
-- #!@& ISE doesn't know VHDL 2008 (... process(all) ...)
-- by default, all values are passed
WbRegs_o <= WbRegsOutput;
-- LOAD_EXT inputs are overwritten by local registers
WbRegs_o.control_clock_selection_o <= control_clock_selection;
WbRegs_o.control_ch1_mode_o <= control_ch1_mode;
WbRegs_o.control_ch2_mode_o <= control_ch2_mode;
WbRegs_o.vcxo_voltage_o <= vcxo_voltage;
WbRegs_o.clock_divider_hi_o <= clock_divider_hi;
WbRegs_o.clock_ratio_m1_o <= clock_ratio_m1;
WbRegs_o.ch1_delay_set_o <= ch1_delay_set;
WbRegs_o.ch1_delay_reset_o <= ch1_delay_reset;
WbRegs_o.ch2_delay_set_o <= ch2_delay_set;
......@@ -232,11 +221,10 @@ begin
WbRegs_o.trigger_threshold_o <= trigger_threshold;
WbRegs_o.overflow_o <= overflow;
WbRegs_o.trigger_latency_o <= trigger_latency;
WbRegs_o.control_clock_selection_load_o <= control_clock_selection_load;
WbRegs_o.control_ch1_mode_load_o <= control_ch1_mode_load;
WbRegs_o.control_ch2_mode_load_o <= control_ch2_mode_load;
WbRegs_o.vcxo_voltage_load_o <= vcxo_voltage_load;
WbRegs_o.clock_divider_hi_load_o <= clock_divider_hi_load;
WbRegs_o.clock_ratio_m1_load_o <= clock_ratio_m1_load;
WbRegs_o.ch1_delay_set_load_o <= ch1_delay_set_load;
WbRegs_o.ch1_delay_reset_load_o <= ch1_delay_reset_load;
WbRegs_o.ch2_delay_set_load_o <= ch2_delay_set_load;
......
......@@ -76,7 +76,7 @@ begin
)
port map (
Clk_ik => clk_sys_i,
Reset_ir => rst_i,
Reset_ira => rst_i,
Wb_i => WbMosi,
Wb_o => WbMiso,
ClkIn0_ik => ClkIn0_ik,
......
......@@ -25,6 +25,7 @@ vcom -2008 -reportprogress 300 -work work ../../rtl/ShiftRegister.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/ResetSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/Delay.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/EdgeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/ChangeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/Reg.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/RegSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/SlowToggle.vhd
......@@ -35,8 +36,7 @@ vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/module
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/Ad9512Control.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
......@@ -51,8 +51,8 @@ vcom -2008 -reportprogress 300 -work work ../../rtl/WbSlaveWrapper.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayController.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/ClkRfDomain.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/Ad9512Syncer.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/FfpgSlave.vhd
......
......@@ -8,25 +8,23 @@ add wave -group WbSlave -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cWbSlaveWrapp
add wave -group DacsController sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDacsController/*
add wave -group DelayController -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayController/*
add wave -group DelayedPulseGeneratorCh1 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cFsm/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group AddressEnableCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cAddressEnableCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group AddressCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cAddressCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cStreamCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cBitCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cShiftRegisterSet/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cShiftRegisterReset/*
add wave -group DelayedPulseGeneratorCh2 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cFsm/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group AddressEnableCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cAddressEnableCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group AddressCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cAddressCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cStreamCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cBitCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cShiftRegisterSet/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cShiftRegisterReset/*
add wave -group DelayedPulseGeneratorsCdc sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cFsm/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cBitCounter/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cStreamCounter/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cShiftRegisterSet/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cShiftRegisterReset/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cFsm/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cBitCounter/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cStreamCounter/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cShiftRegisterSet/*
add wave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cShiftRegisterReset/*
configure wave -namecolwidth 217
configure wave -valuecolwidth 100
......
......@@ -36,15 +36,6 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Clock source selection in progress";
description = "Status of the clock source selection configuration\n0: configuration done\n1: configuration in progress";
prefix = "clock_selection_busy";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Delay configuration in progress";
description = "Status of the delay configuration\n0: configuration done\n1: configuration in progress";
......@@ -97,13 +88,12 @@ peripheral {
field {
name = "Clock source selection";
description = "0 (default): external clock used (connector on the front panel)\n1: FPGA loop clock used\n2: onboard clock used";
description = "0 (default): external clock used (connector on the front panel)\n1: FPGA loop clock used\n2: on-board VCXO clock used";
prefix = "clock_selection";
type = SLV;
size = 2;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_ONLY;
};
field {
......@@ -178,26 +168,14 @@ peripheral {
};
reg {
name = "Clock divider";
prefix = "clock_divider";
description = "LOw and HIgh values of the AD9512 clock divider - these values are used for all clocks generated on the FMC card. Write both values at one WB transaction, or write LO first and HI last. Clock configuration of both values begins when HI value is written.";
field {
name = "Clock divider LO value";
description = "Number of clock cycles output stays low.";
prefix = "lo";
type = UNSIGNED;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
name = "Clock ratio-1 register";
prefix = "clock_ratio_m1";
description = "Clock ratio specifies the frequency of the serial stream clock generated by the AD9512 clock divider: f_generated = f_input / (RATIO+1). This ratio is used for all clocks generated on the FMC card. Permitted values are 0-31 which renders to actual ratio 1-32.";
field {
name = "Clock divider HI value";
description = "Number of clock cycles output stays high.";
prefix = "hi";
name = "Clock ratio-1";
type = UNSIGNED;
size = 4;
size = 5;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......
......@@ -167,45 +167,6 @@ module Testbench;
$display("[0x%x]: 0x%x", address, d[31:0]);
endtask
task automatic TestSpi;
uint64_t d;
uint32_t base;
uint32_t address;
address = `WB_FFPG_SPI_REG(`SPI_CTRL);
$display("Control reg. write:");
d = 'h2618; // ASS, NEG_TX/RX, LEN=24
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_SPI_REG(`SPI_DIVIDER);
$display("Divider reg. write:");
d = 2; // f_SCLK ~ 20.833 MHz
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_SPI_REG(`SPI_SS);
$display("SlaveSelect reg. write:");
d = 1;
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_SPI_REG(`SPI_TX_RX_0);
$display("TX reg. write:");
d = 'h80A500; // READ register 0xA5
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_SPI_REG(`SPI_CTRL);
$display("Control reg. write:");
d = 'h2718; // ASS, NEG_TX/RX, LEN=24 + GO
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
#2us;
endtask
task automatic TestReal;
`include "z:/wb_trace.svh"
#1ms;
......@@ -217,22 +178,32 @@ module Testbench;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h200);
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
#2us
#200us;
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
endtask
task automatic WaitUntilRead;
uint32_t data;
do
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS), data);
while (data & 'b1111);
endtask
initial begin
acc = new(VME);
#10us; // for PLL lock and reset settle
#20us;
init_vme64x_core;
WaitUntilRead;
// TestSdb;
// TestFfpgCsr;
// TestSpi;
// TestReal;
TestAd9512Sync;
TestAd9512Sync;
// uint64_t blt_addr[];
// uint64_t blt_data[];
......
......@@ -27,6 +27,7 @@ vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ShiftRegister.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ResetSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Delay.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/EdgeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ChangeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Reg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/RegSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/SlowToggle.vhd
......@@ -37,8 +38,7 @@ vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/module
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Ad9512Control.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
......
......@@ -392,15 +392,15 @@
</file>
<file xil_pn:name="../../ffpg/rtl/DacsController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ffpg/rtl/WbSlaveWrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
......@@ -476,7 +476,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
......@@ -486,14 +486,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
......@@ -508,11 +500,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
......@@ -552,7 +544,7 @@
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
......@@ -620,7 +612,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
......@@ -636,7 +628,7 @@
</file>
<file xil_pn:name="../../ffpg/rtl/SlowToggle.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
......@@ -651,12 +643,20 @@
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ffpg/rtl/Ad9512Syncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ffpg/rtl/Ad9512Control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ffpg/rtl/ChangeDetector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
</files>
<bindings>
......
......@@ -124,86 +124,28 @@ def WaitForNotBusy(register, bit, timeOut, tries, message = '', polarity = 1):
if busy:
raise Exception('WaitForNotBusy error: '+message)
###################################################################
## SPI functions
###################################################################
def SpiInit():
WbWrite('spi_divider', 2) # up to 150 MHz of FPGA system clock
WbWrite('spi_ctrl', 0x2618)
WbWrite('spi_ss', 1)
def SpiRead(register):
WaitForNotBusy('spi_ctrl', 8, 0.001, 2, 'SPI read')
inst = 0x800000 | ((register & 0xff) << 8)
WbWrite('spi_tx_rx_0', inst)
WbSetBits('spi_ctrl', 0x100, 0x100)
return WbRead('spi_tx_rx_0')
def SpiWrite(register, data):
WaitForNotBusy('spi_ctrl', 8, 0.001, 2, 'SPI write')
inst = 0x000000 | ((register & 0xff) << 8) | (data & 0xff)
WbWrite('spi_tx_rx_0', inst)
WbSetBits('spi_ctrl', 0x100, 0x100)
###################################################################
## FFPG specific functions
###################################################################
def Ad9512Init():
# power down unused output (OUT2)
SpiWrite(0x3f, 0x03)
# fine delay
# SpiWrite(0x34, 0x0) # use fine delay
# delay = 1 # 0-31
# SpiWrite(0x36, (delay&0x1f)<<1) # set fine delay
# select CLK1 input, power down CLK2 input
SpiWrite(0x45, 0x05)
# output frequency 200 MHz (divide by 2)
SpiWrite(0x4a, 0x00) # OUT0
SpiWrite(0x4c, 0x00) # OUT1
SpiWrite(0x4e, 0x00) # OUT2
SpiWrite(0x50, 0x00) # OUT3
SpiWrite(0x52, 0x00) # OUT4
# phase 0
SpiWrite(0x4b, 0x00) # OUT0
SpiWrite(0x4d, 0x00) # OUT1
SpiWrite(0x4f, 0x00) # OUT2
SpiWrite(0x51, 0x00) # OUT3
SpiWrite(0x53, 0x00) # OUT4
# function pin as sync
SpiWrite(0x58, 0x20)
# confirm write
SpiWrite(0x5a, 1)
# synchronize dividers
# synchronize AD9512 dividers
def Ad9512Sync():
WbSetBits('control', 0x200)
# 0 - front panel clock
# 1 - FPGA loop clock
# 2 - oscillator
def SelectClock(clock):
if clock == 0:
# select CLK1 input, power down CLK2 input (AD9512)
SpiWrite(0x45, 0x05)
# confirm write
SpiWrite(0x5a, 1)
elif clock == 1:
# select CLK2 input, power down CLK1 input (AD9512)
SpiWrite(0x45, 0x02)
# confirm write
SpiWrite(0x5a, 1)
# select IN0 (SY58017)
WbSetBits('control', 3, 0)
elif clock == 2:
# select CLK2 input, power down CLK1 input (AD9512)
SpiWrite(0x45, 0x02)
# confirm write
SpiWrite(0x5a, 1)
# select IN1 (SY58017)
WbSetBits('control', 3, 1)
else:
if (clock < 0) or (clock > 2):
raise Exception("Unknown clock!")
WbSetBits('control', 3, clock)
# ratio 1-32
def SetRatio(ratio):
if (ratio < 1) or (ratio > 32):
raise Exception("Bad ratio!")
# TODO: address has to be changed from 'clock_divider' to 'clock_ratio_m1' with new version of the driver
WbWrite('clock_divider', ratio-1)
# voltage in [V]
def SetTriggerThreshold(voltage):
......@@ -322,12 +264,11 @@ def Status():
PrintBit(status, 0, 'Clock infrastructure configuration', 'busy', 'idle')
PrintBit(status, 1, 'VCXO DAC', 'busy', 'idle')
PrintBit(status, 2, 'Trigger threshold DAC', 'busy', 'idle')
PrintBit(status, 3, 'Clock selection', 'busy', 'idle')
PrintBit(status, 4, 'Delay configuration', 'busy', 'idle')
PrintBit(status, 5, 'Channel 1 output', 'enabled', 'disabled')
PrintBit(status, 6, 'Channel 2 output', 'enabled', 'disabled')
PrintBit(status, 7, 'Channel 1', 'running', 'stopped')
PrintBit(status, 8, 'Channel 2', 'running', 'stopped')
PrintBit(status, 3, 'Delay configuration', 'busy', 'idle')
PrintBit(status, 4, 'Channel 1 output', 'enabled', 'disabled')
PrintBit(status, 5, 'Channel 2 output', 'enabled', 'disabled')
PrintBit(status, 6, 'Channel 1', 'running', 'stopped')
PrintBit(status, 7, 'Channel 2', 'running', 'stopped')
def Control():
print('Control register: ')
......@@ -454,10 +395,10 @@ def OneWireReadRom(overdrive = 0):
def Init(memoryPart = -1):
WbWrite('control', 0)
SpiInit()
Ad9512Init()
SetTriggerThreshold(0.5)
SelectClock(0)
SetRatio(2)
Ad9512Sync()
SetTriggerThreshold(0.5)
SetVcxoFrequency(-0.2105) # 125.0000 MHz
ClearMemory(0, '*', memoryPart)
......@@ -503,7 +444,8 @@ def TestPulse(channel = 1, overflow = 17820):
pulseDelay = 10 # inter-bunch pulse delay in [ns]
pulseWidth = 10 # inter-bunch pulse width in [ns]
bunches = (0,1,2,10,50) # in which bunches pulse should be
bunches = range(overflow / RF_2_BUNCH_RATIO)
# bunches = range(overflow / RF_2_BUNCH_RATIO)
# bunches = (0,)
(setBit, resBit) = SetPulseShape(channel, pulseDelay, pulseWidth)
for bunch in bunches:
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment