Commit a123e07c authored by Jan Pospisil's avatar Jan Pospisil

added readme.txt

parent abaf1726
1) Git - make sure submodules are updated
2) make Wishbone slaves:
mkdir .\doc\manual\svec
cd .\hdl\svec\wb_gen
make carrier_csr
cd ..\..\ffpg\wb_gen
make ffpg_csr
3) in .\hdl\ffpg\rtl\ffpg_csr.vhd add this function before function "function "or" (left, right: t_ffpg_in_registers) return t_ffpg_in_registers":
function f_x_to_zero (x: unsigned) return unsigned is begin
return unsigned(f_x_to_zero(std_logic_vector(x)));
end function;
X) synthesize .\hdl\svec\syn\SvecFfpg.xise
\ No newline at end of file
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