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FMC DEL 1ns 2cha
Commit 8f0c84ef authored by Jan Pospisil's avatar Jan Pospisil
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non-tabifying

parent 475932c2
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Showing with 45 additions and 45 deletions
hdl/ffpg/rtl/DacsController.vhd
View file @ 8f0c84ef
......@@ -24,17 +24,17 @@ end entity;
architecture syn of DacsController is
--! computes least possible width of the vector to store value X
-- http://stackoverflow.com/a/12751341/615627
function log2(X: positive) return natural is
variable Result: natural;
begin
Result := 0;
while (2**Result < X) loop
Result := Result + 1;
end loop;
return Result;
end function;
--! computes least possible width of the vector to store value X
-- http://stackoverflow.com/a/12751341/615627
function log2(X: positive) return natural is
variable Result: natural;
begin
Result := 0;
while (2**Result < X) loop
Result := Result + 1;
end loop;
return Result;
end function;
function f_calculateSclkDivsel(ClkFrequency, DacFrequencyMax: positive) return std_logic_vector is
variable Result: integer;
......
hdl/ffpg/rtl/ResetSyncer.vhd
View file @ 8f0c84ef
......@@ -2,40 +2,40 @@ library ieee;
use ieee.std_logic_1164.all;
entity ResetSyncer is
generic (
g_Length: integer := 3;
g_Inverted: boolean := FALSE
);
port (
Clk_ik: in std_logic;
Reset_ira: in std_logic;
Reset_or: out std_logic
);
generic (
g_Length: integer := 3;
g_Inverted: boolean := FALSE
);
port (
Clk_ik: in std_logic;
Reset_ira: in std_logic;
Reset_or: out std_logic
);
end entity;
architecture syn of ResetSyncer is
function if_sl(condition: boolean; pos: std_logic; neg: std_logic) return std_logic is begin
if condition then
return pos;
else
return neg;
end if;
end function;
function if_sl(condition: boolean; pos: std_logic; neg: std_logic) return std_logic is begin
if condition then
return pos;
else
return neg;
end if;
end function;
attribute ASYNC_REG: string;
attribute ASYNC_REG: string;
attribute KEEP:string;
attribute SHREG_EXTRACT: string;
constant c_Inversion: std_logic := if_sl(g_Inverted, '1', '0');
constant c_Inversion: std_logic := if_sl(g_Inverted, '1', '0');
signal ShiftRegister0: std_logic := ('1' xor c_Inversion);
signal ShiftRegister1: std_logic := ('1' xor c_Inversion);
signal ShiftRegister2: std_logic := ('1' xor c_Inversion);
signal ShiftRegister0: std_logic := ('1' xor c_Inversion);
signal ShiftRegister1: std_logic := ('1' xor c_Inversion);
signal ShiftRegister2: std_logic := ('1' xor c_Inversion);
attribute ASYNC_REG of ShiftRegister0: signal is "true";
attribute ASYNC_REG of ShiftRegister1: signal is "true";
attribute ASYNC_REG of ShiftRegister2: signal is "true";
attribute ASYNC_REG of ShiftRegister0: signal is "true";
attribute ASYNC_REG of ShiftRegister1: signal is "true";
attribute ASYNC_REG of ShiftRegister2: signal is "true";
attribute KEEP of ShiftRegister0: signal is "true";
attribute KEEP of ShiftRegister1: signal is "true";
attribute KEEP of ShiftRegister2: signal is "true";
......@@ -45,18 +45,18 @@ architecture syn of ResetSyncer is
begin
pSyncer: process (Clk_ik, Reset_ira) begin
if Reset_ira = ('1' xor c_Inversion) then
ShiftRegister0 <= ('1' xor c_Inversion);
ShiftRegister1 <= ('1' xor c_Inversion);
ShiftRegister2 <= ('1' xor c_Inversion);
elsif rising_edge(Clk_ik) then
pSyncer: process (Clk_ik, Reset_ira) begin
if Reset_ira = ('1' xor c_Inversion) then
ShiftRegister0 <= ('1' xor c_Inversion);
ShiftRegister1 <= ('1' xor c_Inversion);
ShiftRegister2 <= ('1' xor c_Inversion);
elsif rising_edge(Clk_ik) then
ShiftRegister0 <= ('0' xor c_Inversion);
ShiftRegister1 <= ShiftRegister0;
ShiftRegister2 <= ShiftRegister1;
end if;
end process;
Reset_or <= ShiftRegister2;
end if;
end process;
Reset_or <= ShiftRegister2;
end architecture;
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