Commit f34f48b6 authored by Jan Pospisil's avatar Jan Pospisil

added edge detector for trigger input

parent a123e07c
......@@ -55,7 +55,7 @@ architecture syn of DelayedPulseGeneratorsCdc is
-- ClkRf clock domain
signal ResetRf_r: std_logic;
signal TriggerRf: std_logic;
signal TriggerRf, TriggerRfPulse: std_logic;
signal Ch1RunningRf: std_logic;
signal Ch2RunningRf: std_logic;
signal OverflowRf_b: unsigned(Overflow_ib16'range);
......@@ -90,6 +90,13 @@ begin
Data_ob(0) => TriggerRf
);
cTriggerEdgeDetector: entity work.EdgeDetector(rising)
port map (
Clk_ik => ClkRf_ik,
Signal_i => TriggerRf,
Edge_o => TriggerRfPulse
);
Overflow_b_slv <= std_logic_vector(Overflow_ib16);
cOverflowSyncer: entity work.RegSyncer(syn)
port map (
......@@ -157,7 +164,7 @@ begin
ResMemData_ib32 => Ch1ResMemData_ib32,
ResMemReadStrobe_o => Ch1ResMemReadStrobe_o,
Running_o => Ch1RunningRf,
Trigger_i => TriggerRf,
Trigger_i => TriggerRfPulse,
SetStream_o => Ch1SetStream_o,
ResetStream_o => Ch1ResetStream_o,
FsmState_o => Ch1FsmState_o
......@@ -178,7 +185,7 @@ begin
ResMemData_ib32 => Ch2ResMemData_ib32,
ResMemReadStrobe_o => Ch2ResMemReadStrobe_o,
Running_o => Ch2RunningRf,
Trigger_i => TriggerRf,
Trigger_i => TriggerRfPulse,
SetStream_o => Ch2SetStream_o,
ResetStream_o => Ch2ResetStream_o,
FsmState_o => Ch2FsmState_o
......
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