fixed WB register "trigger latency" handling

f66860fa · Jan Pospisil · 9fa27f2e · f66860fa
Commit f66860fa authored Aug 16, 2016 by Jan Pospisil
Hide whitespace changes
Inline Side-by-side

Showing with 3 additions and 2 deletions

WbSlaveWrapper.vhd hdl/ffpg/rtl/WbSlaveWrapper.vhd +3 -2

No files found.
--- a/hdl/ffpg/rtl/WbSlaveWrapper.vhd
+++ b/hdl/ffpg/rtl/WbSlaveWrapper.vhd
@@ -170,7 +170,7 @@ begin
    end process;
    
    pInputRegisters: process (WbRegs_i, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency) is begin
-        -- #!@& ISE doesn't know VHDL 2008
+        -- #!@& ISE doesn't know VHDL 2008 (... process (all) ...)
        -- by default, all values are passed
        WbRegsInput <= WbRegs_i;
        -- LOAD_EXT inputs are overwritten by local registers
@@ -188,7 +188,7 @@ begin
        WbRegsInput.trigger_latency_i <= trigger_latency;
    end process;
    
-    pOutputRegisters: process (WbRegsOutput, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, control_clock_selection_load, control_ch1_mode_load, control_ch2_mode_load, vcxo_voltage_load, clock_divider_hi_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, trigger_latency_load) is begin
+    pOutputRegisters: process (WbRegsOutput, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency, control_clock_selection_load, control_ch1_mode_load, control_ch2_mode_load, vcxo_voltage_load, clock_divider_hi_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, trigger_latency_load) is begin
        -- #!@& ISE doesn't know VHDL 2008 (... process(all) ...)
        -- by default, all values are passed
        WbRegs_o <= WbRegsOutput;
@@ -204,6 +204,7 @@ begin
        WbRegs_o.ch2_delay_reset_o <= ch2_delay_reset;
        WbRegs_o.trigger_threshold_o <= trigger_threshold;
        WbRegs_o.overflow_o <= overflow;
+        WbRegs_o.trigger_latency_o <= trigger_latency;
        WbRegs_o.control_clock_selection_load_o <= control_clock_selection_load;
        WbRegs_o.control_ch1_mode_load_o <= control_ch1_mode_load;
        WbRegs_o.control_ch2_mode_load_o <= control_ch2_mode_load;