added EdgeDetector architecture for both edges detection; added TODO

a84dd5bc · Jan Pospisil · 9faab5c0 · a84dd5bc · a84dd5bc
Commit a84dd5bc authored Aug 22, 2016 by Jan Pospisil
Hide whitespace changes
Inline Side-by-side

Showing with 19 additions and 1 deletion

EdgeDetector.vhd hdl/ffpg/rtl/EdgeDetector.vhd +17 -1

FFPG_driver.py sw/FFPG_driver.py +2 -0

No files found.
--- a/hdl/ffpg/rtl/EdgeDetector.vhd
+++ b/hdl/ffpg/rtl/EdgeDetector.vhd
@@ -39,4 +39,20 @@ begin
 	
 	Edge_o <= not Signal_i and History;
 	
-end architecture;
\ No newline at end of file
+end architecture;
+
+architecture both of EdgeDetector is
+	
+	signal History: std_logic := '0';
+	
+begin
+	
+	pDelay: process (Clk_ik) is begin
+		if rising_edge(Clk_ik) then
+			History <= Signal_i;
+		end if;
+	end process;
+	
+	Edge_o <= Signal_i xor History;
+	
+end architecture;
--- a/sw/FFPG_driver.py
+++ b/sw/FFPG_driver.py
 #!/usr/bin/env python

+# TODO: propper BUSY bits checking
+
 import sys
 import time
 sys.path.append('/usr/local/encore')