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FMC DEL 1ns 2cha

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Last edited by Tom Levens
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Project description

The FMC DEL 1ns 2cha pulse delay module provides two TTL pulse-outputs with independently adjustable delay and pulse width. Pulses are triggered by a common TTL input with adjustable threshold.

The timing is synchronized either to an external reference clock or an internal 125 MHz VCXO (white rabbit compatible). Delay and pulse width can be fine-adjusted with a resolution of 10 ps.

Signal paths have been optimized for low jitter and high frequency pulse repetition rates.

The card has been designed for generating a periodic gating signal for the LHC Schottky Monitor at CERN. In this application it uses the LHC RF frequency (400.789 MHz) as an input clock and revolution frequency (11.245 kHz) as a trigger. In each turn it can be programmed to generate a pulse to enable a HMC547 fast gate in any of the 3564 bunch slots. The pulse width and delay can be adjusted to optimise the measurement. The two output channels provide independent gating of the horizontal and vertical systems of a single LHC beam.

Block diagram

Specifications

Parameter Value
Channels Two independently programmable output channels sharing a clock and trigger input.
Signal connectors SMA for all signals, can be replaced by LEMO 00 if required
FMC connector Low Pin Count (LPC), Vadj >= 2.5V
Input signal level Clock: 150mVpp to 2Vpp.
Trigger: 5V maximum, adjustable input threshold.
Output signal level Clock: 800mVpp square wave.
Output: TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate
Operating modes TBC
Maximum input clock frequency 1.2GHz to clock divider
~200MHz after divider (for SVEC)
Minimum input clock frequency 100 MHz after divider
Clock divider ratio 1..32
Minimum input pulse width Depends on input clock frequency (1x clock period)
Maximum input pulse rate Depends on input clock frequency (1x clock period)
Output pulse width 2ns (min) to maintain 2.5Vpkpk output level
Output pulse spacing Depends on input clock frequency (1x clock period)
Trigger to output delay TBC
Timebase accuracy ±10ppm with onboard VCXO
Delay accuracy TBC
Power consumption P3V3: 1.5 A
P12V: 50 mA

Detailed project information

Contacts

Commercial producers

  • The card is not commercially produced.

General question about project

Project Status

Date Event
04-01-2016 Work on schematics started.
27-01-2016 First version of schematics ready for review.
05-02-2016 Layout started by CERN design office.
08-02-2016 Inclusion of project on OHWR.
15-03-2016 Layout completed.
27-05-2016 First two prototype boards received.
10-08-2016 First prototype boards under test.
12-08-2016 Some small issues found but the board is functional.
03-11-2016 First two prototype boards deployed (on a SVEC) in LHC for control of Schottky Monitor fast gates.
19-01-2017 Module presented at the BI Technical Board (slides).
01-05-2017 Decision to change from surface mount SMA connectors to through hole due to reliability issues. Amphenol 901-10138 selected as a replacement.
22-05-2017 Version 3 design changes finished.
14-09-2017 12 assembled PCBs received and tested.
23-02-2023 After years of successful operation in the LHC Schottky Monitor, the project has been revisited due to a new application at CERN requiring implementation on a SPEC carrier instead of the SVEC. For this the gateway has been ported to the latest SVEC/SPEC base designs.

Michael Betz, Tom Levens, Jan Pospisil - 09 February 2016