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FMC DEL 1ns 2cha
Commit 0d512ced authored by Jan Pospisil's avatar Jan Pospisil
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added default value for lucid beginning of the simulation

parent 933011a5
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Showing with 13 additions and 7 deletions
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
View file @ 0d512ced
......@@ -23,8 +23,8 @@ entity DelayedPulseGenerator is
Running_o: out std_logic;
-- FMC interface
Trigger_i: in std_logic;
SetStream_o: out std_logic;
ResetStream_o: out std_logic;
SetStream_o: out std_logic := '0';
ResetStream_o: out std_logic := '0';
-- debug
FsmState_o: out unsigned(2 downto 0)
);
......@@ -48,11 +48,13 @@ architecture syn of DelayedPulseGenerator is
signal AddressEnableCounterOverflow: std_logic;
signal AddressEnableCounterSetValue: unsigned(TriggerLatency_ib16'range);
signal AddressCounterReset, AddressCounterResetOrReset: std_logic;
signal AddressCounterReset: std_logic := '0';
signal AddressCounterResetOrReset: std_logic;
signal AddressCounterSetValue: unsigned(TriggerLatency_ib16'range);
signal AddressCounterValue: unsigned(SetMemAddress_ob11'range);
signal StreamReset, StreamResetOrReset: std_logic;
signal StreamReset: std_logic := '0';
signal StreamResetOrReset: std_logic;
signal StreamPosition: unsigned(Overflow_ib16'range);
signal BitCounterOverflow, LoadShiftRegister: std_logic;
......
hdl/ffpg/rtl/ShiftRegister.vhd
View file @ 0d512ced
......@@ -27,7 +27,7 @@ end entity;
architecture right of ShiftRegister is
signal Data_b: unsigned(g_Width-1 downto 0);
signal Data_b: unsigned(g_Width-1 downto 0) := (others => '0');
begin
......
hdl/svec/rtl/HeartBeat.vhd
View file @ 0d512ced
......@@ -9,7 +9,7 @@ entity HeartBeat is
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
HeartBeat_o: out std_logic
HeartBeat_o: out std_logic := '0'
);
end entity;
......@@ -51,7 +51,8 @@ architecture syn of HeartBeat is
constant c_DividerWidth: natural := c_ClkFreqWidth - c_PwmWidth;
constant c_DividerLimit: natural := g_ClkFrequency / (2**c_PwmWidth);
signal PwmCountDown, UpdatePwmValue, PwmCounterOverflow: std_logic;
signal PwmCountDown: std_logic := '0';
signal UpdatePwmValue, PwmCounterOverflow: std_logic;
signal PwmCounter_b, PwmValue_b, PwmValue_bd: signed(c_PwmWidth-1 downto 0) := (others => '0');
begin
......
hdl/svec/sim/testbench/Testbench.sv
View file @ 0d512ced
......@@ -46,6 +46,9 @@ module Testbench;
wire CarrierSda_io;
wire CarrierOneWire_io;
pullup(CarrierScl_io);
pullup(CarrierSda_io);
CBusAccessor_VME64x acc;
SvecTopFfpgWrapper cDut (
......
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