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FMC DEL 1ns 2cha
Commit 4a3aa688 authored by Jan Pospisil's avatar Jan Pospisil
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fix AD9512 synchronization - now synchronized by Trigger_i

parent 7c6f7f70
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Showing with 87 additions and 30 deletions
hdl/ffpg/rtl/Ad9512Syncer.vhd 0 → 100644
View file @ 4a3aa688
library ieee;
use ieee.std_logic_1164.all;
entity Ad9512Syncer is
generic (
g_ClkFrequency: positive -- input clock frequency in Hz
);
port (
Clk_ik: in std_logic;
StartSync_i: in std_logic; -- one pulse starts synchronization
Trigger_i: in std_logic; -- falling edge of this signals determines synchronization point
Ad9512Sync_o: out std_logic := '0' -- synchronization pulse for AD9512
);
end entity;
architecture syn of Ad9512Syncer is
signal Pulse, GeneratorReset_ra: std_logic;
begin
-- AD9512 function pin is set as SYNCB - needs negative pulse > 1.5*T_rfClk
-- (f_rfClk >= 1 MHz) => (1.5*T_rfClk <= 1.5 us)
cAd9512SyncPulseGenerator: entity work.PulseGeneratorTime(syn)
generic map (
g_ClkFrequency => g_ClkFrequency,
g_PulseMinWidthInTime => 2 us
)
port map (
Clk_ik => Clk_ik,
Reset_ir => '0',
Signal_i => StartSync_i,
Pulse_o => Pulse
);
GeneratorReset_ra <= Trigger_i and (not Pulse);
pSyncPulseGenerator: process(Clk_ik, GeneratorReset_ra) is begin
if GeneratorReset_ra = '1' then
Ad9512Sync_o <= '0';
elsif rising_edge(Clk_ik) then
if StartSync_i = '1' then
Ad9512Sync_o <= '1';
end if;
end if;
end process;
end architecture;
\ No newline at end of file
hdl/ffpg/rtl/FfpgCore.vhd
View file @ 4a3aa688
......@@ -39,6 +39,7 @@ entity FfpgCore is
Ch1ResLe_o: out std_logic;
Ch2SetLe_o: out std_logic;
Ch2ResLe_o: out std_logic;
--
Ch1Set_o: out std_logic;
Ch1Res_o: out std_logic;
Ch2Set_o: out std_logic;
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ 4a3aa688
......@@ -31,6 +31,7 @@ entity FfpgSlave is
Ch1ResLe_o: out std_logic;
Ch2SetLe_o: out std_logic;
Ch2ResLe_o: out std_logic;
--
Ch1Set_o: out std_logic;
Ch1Res_o: out std_logic;
Ch2Set_o: out std_logic;
......@@ -246,19 +247,15 @@ begin
-- Pulse generator board clocks
----------------------------------
-- Ad9512Func_o is set as SYNCB - need negative pulse > 1.5*T_rfClk
-- (f_rfClk >= 1 MHz) => (1.5*T_rfClk <= 1.5 us)
cAd9512SyncPulseGenerator: entity work.PulseGeneratorTime(syn)
cAd9512Syncer: entity work.Ad9512Syncer(syn)
generic map (
g_ClkFrequency => g_ClkFrequency,
g_PulseMinWidthInTime => 2 us
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Signal_i => WbRegsOutput.control_ad9512_sync_o,
Pulse_o => Ad9512SyncePulse
StartSync_i => WbRegsOutput.control_ad9512_sync_o,
Trigger_i => Trigger_i,
Ad9512Sync_o => Ad9512SyncePulse
);
Ad9512Func_o <= not Ad9512SyncePulse;
......
hdl/ffpg/sim/testbench/make
View file @ 4a3aa688
......@@ -53,6 +53,7 @@ vcom -2008 -reportprogress 300 -work work ../../rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/ClkRfDomain.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/Ad9512Syncer.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/FfpgSlave.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
......
hdl/svec/sim/testbench/Testbench.sv
View file @ 4a3aa688
......@@ -209,8 +209,16 @@ module Testbench;
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_DEBUG), dataOut, "Debug");
endtask
initial begin
task automatic TestAd9512Sync;
uint32_t data;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h200);
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
#2us
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
endtask
initial begin
acc = new(VME);
#10us; // for PLL lock and reset settle
......@@ -221,11 +229,7 @@ module Testbench;
// TestFfpgCsr;
// TestSpi;
// TestReal;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h200);
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
#2us
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
TestAd9512Sync;
// uint64_t blt_addr[];
// uint64_t blt_data[];
......
hdl/svec/sim/testbench/make
View file @ 4a3aa688
......@@ -55,6 +55,7 @@ vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Ad9512Syncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgSlave.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
......
hdl/svec/syn/SvecFfpg.xise
View file @ 4a3aa688
......@@ -380,15 +380,15 @@
<files>
<file xil_pn:name="../rtl/SvecTopFfpg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ffpg/rtl/FfpgCore.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ffpg/rtl/FfpgSlave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DacsController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
......@@ -480,7 +480,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
......@@ -492,7 +492,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
......@@ -516,7 +516,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
......@@ -548,11 +548,11 @@
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
......@@ -612,11 +612,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
......@@ -632,11 +632,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
......@@ -652,7 +652,7 @@
</file>
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ffpg/rtl/SlowToggle.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
......@@ -660,19 +660,23 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="SvecFfpg.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../rtl/HeartBeat.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ffpg/rtl/Ad9512Syncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
</files>
<bindings>
......
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