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FMC DEL 1ns 2cha
Commits
7c6f7f70
Commit
7c6f7f70
authored
Aug 17, 2016
by
Jan Pospisil
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added memory output registers; improved timing
parent
689cba91
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2 changed files
with
30 additions
and
17 deletions
+30
-17
DelayedPulseGenerator.vhd
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
+18
-5
SvecFfpg.xise
hdl/svec/syn/SvecFfpg.xise
+12
-12
No files found.
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
View file @
7c6f7f70
...
...
@@ -32,7 +32,12 @@ end entity;
architecture
syn
of
DelayedPulseGenerator
is
constant
c_MemLatency
:
integer
:
=
2
;
constant
c_MemLatency
:
integer
:
=
2
+
1
;
-- +1 for memory output registers implemented here
-- for memory output registers
signal
SetMemData_b32
:
unsigned
(
SetMemData_ib32
'range
)
:
=
(
others
=>
'0'
);
signal
ResMemData_b32
:
unsigned
(
ResMemData_ib32
'range
)
:
=
(
others
=>
'0'
);
signal
LastStreamPosition
:
unsigned
(
Overflow_ib16
'range
)
:
=
(
others
=>
'0'
);
signal
TriggerLatencyPlusTwo
:
unsigned
(
TriggerLatency_ib16
'range
)
:
=
(
others
=>
'0'
);
...
...
@@ -56,6 +61,14 @@ architecture syn of DelayedPulseGenerator is
begin
-- memory output registers
pMemOutputReg
:
process
(
Clk_ik
)
is
begin
if
rising_edge
(
Clk_ik
)
then
SetMemData_b32
<=
SetMemData_ib32
;
ResMemData_b32
<=
ResMemData_ib32
;
end
if
;
end
process
;
-- for better timing
pInputReg
:
process
(
Clk_ik
)
is
begin
if
rising_edge
(
Clk_ik
)
then
...
...
@@ -173,12 +186,12 @@ begin
cShiftRegisterSet
:
entity
work
.
ShiftRegister
(
right
)
generic
map
(
g_Width
=>
SetMemData_
i
b32
'length
g_Width
=>
SetMemData_b32
'length
)
port
map
(
Clk_ik
=>
Clk_ik
,
Reset_ir
=>
Reset_ir
,
Data_ib
=>
SetMemData_
i
b32
,
Data_ib
=>
SetMemData_b32
,
Data_ob
=>
open
,
Shift_i
=>
'0'
,
Shift_o
=>
SetStream
,
...
...
@@ -188,12 +201,12 @@ begin
cShiftRegisterReset
:
entity
work
.
ShiftRegister
(
right
)
generic
map
(
g_Width
=>
ResMemData_
i
b32
'length
g_Width
=>
ResMemData_b32
'length
)
port
map
(
Clk_ik
=>
Clk_ik
,
Reset_ir
=>
Reset_ir
,
Data_ib
=>
ResMemData_
i
b32
,
Data_ib
=>
ResMemData_b32
,
Data_ob
=>
open
,
Shift_i
=>
'0'
,
Shift_o
=>
ResetStream
,
...
...
hdl/svec/syn/SvecFfpg.xise
View file @
7c6f7f70
...
...
@@ -47,7 +47,7 @@
<property
xil_pn:name=
"Case Implementation Style"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
...
@@ -100,9 +100,9 @@
<property
xil_pn:name=
"Exclude Compilation of Deprecated EDK Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of EDK Sub-Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Cost Tables Map"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Effort (Highest PAR level only)"
xil_pn:value=
"No
rmal"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Extra Effort (Highest PAR level only)"
xil_pn:value=
"No
ne"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"FPGA Start-Up Clock"
xil_pn:value=
"CCLK"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Encoding Algorithm"
xil_pn:value=
"
Auto"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"FSM Encoding Algorithm"
xil_pn:value=
"
Speed1"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"FSM Style"
xil_pn:value=
"LUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Filter Files From Compile Order"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Flatten Output Netlist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -131,7 +131,7 @@
<property
xil_pn:name=
"Generate Verbose Library Compilation Messages"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generics, Parameters"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Optimization Goal"
xil_pn:value=
"AllClockNets"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Optimization map spartan6"
xil_pn:value=
"
Speed"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Global Optimization map spartan6"
xil_pn:value=
"
Off"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Global Set/Reset Port Name"
xil_pn:value=
"GSR_PORT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Tristate Port Name"
xil_pn:value=
"GTS_PORT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"HDL Instantiation Template Target Language"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"default"
/>
...
...
@@ -157,7 +157,7 @@
<property
xil_pn:name=
"JTAG Pin TMS"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Keep Hierarchy"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"LUT Combining Map"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"LUT Combining Xst"
xil_pn:value=
"
Auto"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"LUT Combining Xst"
xil_pn:value=
"
No"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Language"
xil_pn:value=
"All"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Last Applied Goal"
xil_pn:value=
"Balanced"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Last Applied Strategy"
xil_pn:value=
"Xilinx Default (unlocked)"
xil_pn:valueState=
"default"
/>
...
...
@@ -194,7 +194,7 @@
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report Post Trace"
xil_pn:value=
"5"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Optimization Effort spartan6"
xil_pn:value=
"High"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"Speed"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -217,8 +217,8 @@
<property
xil_pn:name=
"Output Extended Identifiers"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Output File Name"
xil_pn:value=
"SvecTopFfpg"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Overwrite Compiled Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"
Auto"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"
For Inputs and Outputs"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"
Yes"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"
Off"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Package"
xil_pn:value=
"fgg900"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -227,7 +227,7 @@
<property
xil_pn:name=
"Place And Route Mode"
xil_pn:value=
"Normal Place and Route"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place MultiBoot Settings into Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Effort Level Map"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Extra Effort Map"
xil_pn:value=
"No
rmal"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Placer Extra Effort Map"
xil_pn:value=
"No
ne"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Port to be used"
xil_pn:value=
"Auto - default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Map Simulation Model Name"
xil_pn:value=
"SvecTopFfpg_map.vhd"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Place & Route Simulation Model Name"
xil_pn:value=
"SvecTopFfpg_timesim.vhd"
xil_pn:valueState=
"default"
/>
...
...
@@ -249,8 +249,8 @@
<property
xil_pn:name=
"Read Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reduce Control Sets"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Regenerate Core"
xil_pn:value=
"Under Current Project Setting"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Balancing"
xil_pn:value=
"
No"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Register Duplication Map"
xil_pn:value=
"O
n"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Register Balancing"
xil_pn:value=
"
Yes"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Register Duplication Map"
xil_pn:value=
"O
ff"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Register Duplication Xst"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Ordering spartan6"
xil_pn:value=
"4"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Release Write Enable (Output Events)"
xil_pn:value=
"Default (6)"
xil_pn:valueState=
"default"
/>
...
...
@@ -318,7 +318,7 @@
<property
xil_pn:name=
"Unused IOB Pins"
xil_pn:value=
"Pull Down"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use 64-bit PlanAhead on 64-bit Systems"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Automatic Do File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Clock Enable"
xil_pn:value=
"
Auto"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Use Clock Enable"
xil_pn:value=
"
Yes"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Use Configuration Name"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Do File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Do File Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
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