TODOs reorganized, added divider generics to OneWire module

811d92b0 · Jan Pospisil · b5dfdd72 · 811d92b0
Commit 811d92b0 authored Aug 16, 2016 by Jan Pospisil
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FfpgCore.vhd hdl/ffpg/rtl/FfpgCore.vhd +8 -4

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--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
 -- TODO:
+--   ! clock dividers synchronization
 --   - automatic clock infrastructure configuration
 --   ? clock selection
 --   ? clock divider
 --   - frequency sense
 --   - timing
--   - clock dividers synchronization
 --   - TEST: TriggerLatency == 0
--   - Trigger_i will be 25 ns long on ClkRf 200 MHz -> edge detector needed!
--   - ClkRfDomain one hierarchy level up (both channels synchronized the same way)

 library ieee;
 use ieee.std_logic_1164.all;
@@ -211,7 +209,13 @@ begin
            g_address_granularity => BYTE,
            g_num_ports => 1,
            g_ow_btp_normal => "5.0",
-            g_ow_btp_overdrive => "1.0"
+            g_ow_btp_overdrive => "1.0",
+            -- CDR_N = f_CLK * BTP_N - 1
+            --   CDR_N = 125MHz * 5.0us - 1 = 625 - 1 = 624 = 0x0270
+            -- CDR_O = f_CLK * BTP_O - 1
+            --   CDR_O = 125MHz * 1.0us - 1 = 125 - 1 = 124 = 0x007C
+            g_CDR_N => 624,
+            g_CDR_O => 124
        )
        port map (
            clk_sys_i => Clk_ik,