added debug register; added FSM state to debug register

9fa27f2e · Jan Pospisil · 33254a7d · 9fa27f2e · 9fa27f2e · 9fa27f2e
Commit 9fa27f2e authored Aug 16, 2016 by Jan Pospisil
6 changed files
--- a/hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
@@ -24,7 +24,9 @@ entity DelayedPulseGenerator is
        -- FMC interface
        Trigger_i: in std_logic;
        SetStream_o: out std_logic;
-        ResetStream_o: out std_logic
+        ResetStream_o: out std_logic;
+        -- debug
+        FsmState_o: out unsigned(2 downto 0)
    );
 end entity;

@@ -74,7 +76,8 @@ begin
            StreamReset_i => StreamReset,
            Running_o => Running_o,
            GenerationEnable_o => GenerationEnable,
-            OutputEnable_o => OutputEnable
+            OutputEnable_o => OutputEnable,
+            State_o => FsmState_o
        );

    -- for better timing

--- a/hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
@@ -39,7 +39,10 @@ entity DelayedPulseGeneratorsCdc is
        Ch1SetStream_o: out std_logic;
        Ch1ResetStream_o: out std_logic;
        Ch2SetStream_o: out std_logic;
-        Ch2ResetStream_o: out std_logic
+        Ch2ResetStream_o: out std_logic;
+        -- debug
+        Ch1FsmState_o: out unsigned(2 downto 0);
+        Ch2FsmState_o: out unsigned(2 downto 0)
    );
 end entity;

@@ -156,7 +159,8 @@ begin
            Running_o => Ch1RunningRf,
            Trigger_i => TriggerRf,
            SetStream_o => Ch1SetStream_o,
-            ResetStream_o => Ch1ResetStream_o
+            ResetStream_o => Ch1ResetStream_o,
+            FsmState_o => Ch1FsmState_o
        );

    cDelayedPulseGeneratorCh2: entity work.DelayedPulseGenerator(syn)
@@ -176,7 +180,8 @@ begin
            Running_o => Ch2RunningRf,
            Trigger_i => TriggerRf,
            SetStream_o => Ch2SetStream_o,
-            ResetStream_o => Ch2ResetStream_o
+            ResetStream_o => Ch2ResetStream_o,
+            FsmState_o => Ch2FsmState_o
        );

    ----------------------------------

--- a/hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
@@ -17,7 +17,9 @@ entity Fsm is
        -- outputs
        Running_o: out std_logic := '0';
        GenerationEnable_o: out std_logic := '0';
-        OutputEnable_o: out std_logic := '0'
+        OutputEnable_o: out std_logic := '0';
+        -- debug
+        State_o: out unsigned(2 downto 0)
    );
 end entity;

@@ -31,6 +33,10 @@ architecture syn of Fsm is
        s_WaitForEnd
    );
    
+    function f_State2Unsigned (State: t_State) return unsigned is begin
+        return to_unsigned(t_State'pos(State), 3);
+    end function;
+
    constant c_ResetState: t_State := s_Stop;
    
    signal State: t_State := c_ResetState;
@@ -100,5 +106,7 @@ begin
            when others => null;
        end case;
    end process;
+    
+    State_o <= f_State2Unsigned(State);

 end architecture;
\ No newline at end of file
--- a/hdl/ffpg/rtl/FfpgSlave.vhd
+++ b/hdl/ffpg/rtl/FfpgSlave.vhd
@@ -187,7 +187,9 @@ begin
            Ch1SetStream_o => Ch1Set_o,
            Ch1ResetStream_o => Ch1Res_o,
            Ch2SetStream_o => Ch2Set_o,
-            Ch2ResetStream_o => Ch2Res_o
+            Ch2ResetStream_o => Ch2Res_o,
+            Ch1FsmState_o => WbRegsInput.debug_i(2 downto 0),
+            Ch2FsmState_o => WbRegsInput.debug_i(5 downto 3)
        );

    ----------------------------------
@@ -253,5 +255,6 @@ begin
    WbRegsInput.status_clock_infrastructure_busy_i <= 'X';
    WbRegsInput.status_clock_selection_busy_i <= 'X';
    WbRegsInput.frequency_i <= (others => 'X');
+    WbRegsInput.debug_i(31 downto 6) <= (others => '0');

 end architecture;
--- a/hdl/ffpg/wb_gen/ffpg_csr.wb
+++ b/hdl/ffpg/wb_gen/ffpg_csr.wb
@@ -326,6 +326,20 @@ peripheral {
    };
  };

+  reg {
+    name = "Debug register";
+    prefix = "debug";
+    description = "For internal use only, do not use!";
+
+    field {
+      name = "Debug field";
+      type = UNSIGNED;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
  ram {
    name = "CH1 SET serial stream";
    prefix = "ch1_set_mem";

--- a/hdl/svec/sim/testbench/Testbench.sv
+++ b/hdl/svec/sim/testbench/Testbench.sv
@@ -206,6 +206,7 @@ module Testbench;
    task automatic TestReal;
        `include "z:/wb_trace.svh"
        #1ms;
+        WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_DEBUG), dataOut, "Debug");
    endtask
    
    initial begin