- 23 Aug, 2016 2 commits
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Jan Pospisil authored
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Jan Pospisil authored
fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave default values (always zeros)
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- 22 Aug, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
added automatic start-up AD9512 configuration; implemented full clock selection feature; added clock division ratio selection; removed AD9512 SPI slave; fixed FFPG simulation scripts
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Jan Pospisil authored
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- 18 Aug, 2016 9 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation
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Jan Pospisil authored
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Jan Pospisil authored
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- 17 Aug, 2016 5 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 16 Aug, 2016 13 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
fixed integer division in DAC functions; added errors report in SV trace debug; added Enable/Disable and Start/Stop functions
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Jan Pospisil authored
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- 15 Aug, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 12 Aug, 2016 3 commits
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Jan Pospisil authored
merged CDC for both channels in one entity, common signals have single CDC; changed LED blinking frequency 5 Hz -> 15 Hz
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Jan Pospisil authored
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Jan Pospisil authored
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