The SVEC base design has constraints for gc_sync_register but this is
never instantiated in this design. Therefore ISE gives an error during
synthesis.

To avoid this error I have added an extra "dummy" gc_sync_register for
synchronising the FP GPIO inputs. This can be removed once this issue
is resolved:

https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25

References:
    https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec
    https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/wrtd-reference-designs

Ensure transition to stop state only happens at end of sequence and that
start only happens when stopped.

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