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F
FMC DEL 1ns 2cha
Commit f7b7c9a0 authored by Tom Levens's avatar Tom Levens
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Update FSM 

Ensure transition to stop state only happens at end of sequence and that
start only happens when stopped.
parent e502f504
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Showing with 8 additions and 6 deletions
hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
View file @ f7b7c9a0
......@@ -70,16 +70,14 @@ architecture syn of Fsm is
return to_unsigned(t_State'pos(State), 3);
end function;
constant c_ResetState: t_State := s_Stop;
signal State: t_State := c_ResetState;
signal State: t_State := s_Stop;
begin
pFsmTransitions: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
State <= c_ResetState;
State <= s_Stop;
else
State <= State;
if ModeLoad_i = '1' then
......@@ -94,6 +92,10 @@ begin
else
-- separate states
case State is
when s_Stop =>
if (ModeLoad_i = '1') and (Mode_i /= e_ModeStop) then
State <= s_WaitForTrigger;
end if;
when s_WaitForTrigger =>
if Trigger_i = '1' then
State <= s_Generating;
......@@ -103,11 +105,11 @@ begin
State <= s_Outputting;
end if;
when s_Outputting =>
if (StreamReset_i = '1') and (Mode_i = e_ModeSingle) then
if (StreamReset_i = '1') and ((Mode_i = e_ModeSingle) or (Mode_i = e_ModeStop)) then
State <= s_Stop;
end if;
when others =>
State <= c_ResetState;
State <= s_Stop;
end case;
end if;
end if;
......
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