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FMC DEL 1ns 2cha
Commit a3dc2ea8 authored by Tom Levens's avatar Tom Levens
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Port to latest SVEC reference design 

References:
    https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec
    https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/wrtd-reference-designs
parent 0ca74d29
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.gitmodules
View file @ a3dc2ea8
......@@ -2,13 +2,16 @@
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
branch = proposed_master
[submodule "hdl/ip_cores/wishbone-gen"]
path = hdl/ip_cores/wishbone-gen
url = https://ohwr.org/project/wishbone-gen.git
[submodule "hdl/ip_cores/uvm_agents"]
path = hdl/ip_cores/uvm_agents
url = https://github.com/AakaFosfor/uvm_agents.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
branch = proposed_master
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
hdl/ffpg/rtl/Ad9512Control.vhd
View file @ a3dc2ea8
......@@ -386,7 +386,7 @@ begin
wb_cyc_i => WbStb,
wb_ack_o => WbAck,
wb_err_o => open,
wb_int_o => WbInt,
int_o => WbInt,
ss_pad_o => SpiAd9512Cs_n,
sclk_pad_o => SpiAd9512Sclk_o,
mosi_pad_o => SpiAd9512Mosi_o,
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ a3dc2ea8
......@@ -292,7 +292,6 @@ begin
CnxMasterIn(c_SlaveAd9512Id).err <= '0';
CnxMasterIn(c_SlaveAd9512Id).rty <= '0';
CnxMasterIn(c_SlaveAd9512Id).stall <= '0';
CnxMasterIn(c_SlaveAd9512Id).int <= '0';
SpiAd9512CsWb_n <= ChipSelect_b32(0);
----------------------------------
......
hdl/ffpg/rtl/FfpgPkg.vhd
View file @ a3dc2ea8
......@@ -40,9 +40,9 @@ use work.wishbone_pkg.all;
package FfpgPkg is
constant VersionMajor: natural := 1;
constant VersionMinor: natural := 4;
constant VersionRevision: natural := 2;
constant VersionMajor: natural := 2;
constant VersionMinor: natural := 0;
constant VersionRevision: natural := 0;
type t_Ad5600Interface is record
FrameSynchronization_n: std_logic;
......
hdl/ffpg/rtl/Manifest.py
View file @ a3dc2ea8
......@@ -2,8 +2,28 @@ files = [
"ffpg_csr.vhd",
"ffpg_csr_pkg.vhd",
"FfpgCore.vhd",
"FfpgCorePkg.vhd",
"../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
"FfpgPkg.vhd",
"FfpgSlave.vhd",
"Ad9512Control.vhd",
"Ad9512Syncer.vhd",
"ChangeDetector.vhd",
"CounterLength.vhd",
"Counter.vhd",
"DacsController.vhd",
"DelayController.vhd",
"DelayedPulseGenerator/DelayedPulseGeneratorFsm.vhd",
"DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd",
"DelayedPulseGenerator/DelayedPulseGenerator.vhd",
"Delay.vhd",
"EdgeDetector.vhd",
"FrequencySense.vhd",
"PulseGeneratorTime.vhd",
"PulseGenerator.vhd",
"RegSyncer.vhd",
"Reg.vhd",
"ResetSyncer.vhd",
"ShiftRegister.vhd",
"SlowToggle.vhd",
"SpiMasterWb.v",
"WbSlaveWrapper.vhd",
]
modules = { "local" : ["../../ip_cores/wishbone-gen/lib"]}
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ a3dc2ea8
......@@ -138,7 +138,6 @@ begin
);
Wb_o.err <= '0';
Wb_o.rty <= '0';
Wb_o.int <= '0';
-- local registers for LOAD_EXT fields
pLocalRegs: process (Clk_ik) is begin
......
ddr3-sp6-core @ 01a07e1d
Subproject commit 01a07e1d6d118c0a9afc4a4a3c009bfc2027abca
general-cores @ 902c347a
Subproject commit 0d75c0fdc0059b9ce3a8adb76a4ff14b5b795d6c
Subproject commit 902c347af55ae3c4c3e19ba6646b0cd83f76a8e8
svec @ 190e95de
Subproject commit 190e95decc6f79b14eb34761bf28f600e9063e24
uvm_agents @ 0b05a55f
Subproject commit 0b05a55f2b73ecd210f7de4e278c394e314bb5f9
vme64x-core @ a0ca042e
Subproject commit 52d537441e6187619dee7b908534d72408cc03f0
Subproject commit a0ca042e1f3c19a81c3594477c0c811ac761aaa4
wishbone-gen @ 8d431e7f
Subproject commit 8d431e7f4dbd9e2423b3207267c7495df64e27b0
hdl/ip_cores/wishbone-gen_patches/0001-updated-README-wbgen2-seems-not-to-work-in-Lua-5.1.x.patch deleted 100644 → 0
View file @ 0ca74d29
From dabd1b3d6d05cc844ae576701b69b0a535be1748 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 18:43:20 +0200
Subject: [PATCH 1/7] updated README - wbgen2 seems not to work in Lua > 5.1.x
---
README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/README b/README
index 6081554..705c954 100644
--- a/README
+++ b/README
@@ -1,4 +1,4 @@
-This is the initial version of wbgen2. Requires Lua 5.1.4+. Enjoy it :)
+This is the initial version of wbgen2. Requires Lua 5.1.x (not 5.2.x and newer). Enjoy it :)
Compilation instructions:
Just type "make" in the main directory of wbgen2. The resulting file will be "wbgen2".
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0002-added-an-error-for-unsupported-Verilog-option.patch deleted 100644 → 0
View file @ 0ca74d29
From 6fac46f32b9791f6041a8aa7900dc125c11faa4c Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 18:44:54 +0200
Subject: [PATCH 2/7] added an error for unsupported Verilog option
---
wbgen_main.lua | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/wbgen_main.lua b/wbgen_main.lua
index 02fb2ec..9dfec6e 100644
--- a/wbgen_main.lua
+++ b/wbgen_main.lua
@@ -18,7 +18,13 @@
-- MA 02111-1307, USA.
--
-wbgen2_version="0.6.1-alpha"
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * added an error for unsupported Verilog option
+--------------------------------------------------------------------------------
+
+wbgen2_version="0.6.2-alpha"
options = {};
options.reset_type = "asynchronous";
@@ -191,6 +197,7 @@ if(options.output_hdl_file ~= nil) then
if (options.lang == "vhdl") then
cgen_generate_vhdl_code(tree);
elseif (options.lang == "verilog") then
+ die("Verilog option is not supported")
-- cgen_generate_verilog_code(tree);
end
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0003-better-indent-for-VHDL-package.patch deleted 100644 → 0
View file @ 0ca74d29
From 09e2f21902515eb35c19b75f0550b034a20c1165 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 19:09:21 +0200
Subject: [PATCH 3/7] better indent for VHDL package
---
cgen_common.lua | 12 +++++++++---
cgen_vhdl.lua | 47 ++++++++++++++++++++++++++++++++++++++---------
2 files changed, 47 insertions(+), 12 deletions(-)
diff --git a/cgen_common.lua b/cgen_common.lua
index dca15cd..7c77c7a 100644
--- a/cgen_common.lua
+++ b/cgen_common.lua
@@ -5,6 +5,11 @@
-- CERN BE-CO-HT
-- LICENSED UNDER GPL v2
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * better indent for VHDL package
+--------------------------------------------------------------------------------
------------------------------
-- HDL syntax tree constructors
@@ -345,6 +350,9 @@ function indent_zero()
end
function indent_left()
+ if cur_indent <= 0 then
+ die("internal error - unmatched indent")
+ end
cur_indent = cur_indent - 1;
end
@@ -363,9 +371,7 @@ function emiti()
end
function emit(s)
- local i;
-
- for i = 1,cur_indent do emit_code=emit_code.." "; end
+ emiti();
emit_code=emit_code..s.."\n";
end
diff --git a/cgen_vhdl.lua b/cgen_vhdl.lua
index 80e91c9..1bafa9b 100644
--- a/cgen_vhdl.lua
+++ b/cgen_vhdl.lua
@@ -8,6 +8,12 @@
-- The VHDL code generator.
--
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * better indent for VHDL package
+--------------------------------------------------------------------------------
+
-- conversion table between VHDL data types and wbgen2 internal data types
fieldtype_2_vhdl={};
fieldtype_2_vhdl[BIT]="std_logic";
@@ -69,13 +75,11 @@ function cgen_vhdl_package()
local pkg_name = periph.hdl_prefix.."_wbgen2_pkg";
emit("package "..pkg_name.." is")
indent_right();
- emit("");
-
emit("");
emit("-- Input registers (user design -> WB slave)");
emit("");
-
+
cgen_vhdl_port_struct("in");
emit("");
@@ -83,51 +87,72 @@ function cgen_vhdl_package()
emit("");
cgen_vhdl_port_struct("out");
-
-
- indent_left();
+ emit("");
+ emit("-- functions");
+ emit("");
local typename = "t_"..periph.hdl_prefix.."_in_registers";
emit("function \"or\" (left, right: "..typename..") return "..typename..";");
emit("function f_x_to_zero (x:std_logic) return std_logic;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector;");
+ emit("");
indent_left();
- indent_left();
emit("end package;");
emit("");
emit("package body "..pkg_name.." is");
+ indent_right();
+ emit("");
emit("function f_x_to_zero (x:std_logic) return std_logic is");
emit("begin")
+ indent_right();
emit("if x = '1' then")
+ indent_right();
emit("return '1';")
+ indent_left();
emit("else")
+ indent_right();
emit("return '0';")
+ indent_left();
emit("end if;")
+ indent_left();
emit("end function;");
+ emit("");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
+ indent_right();
emit("variable tmp: std_logic_vector(x'length-1 downto 0);");
+ indent_left();
emit("begin");
+ indent_right();
emit("for i in 0 to x'length-1 loop");
+ indent_right();
emit("if(x(i) = 'X' or x(i) = 'U') then");
+ indent_right();
emit("tmp(i):= '0';");
+ indent_left();
emit("else");
+ indent_right();
emit("tmp(i):=x(i);");
+ indent_left();
emit("end if; ");
+ indent_left();
emit("end loop; ");
emit("return tmp;");
+ indent_left();
emit("end function;");
-
-
+ emit("");
emit("function \"or\" (left, right: "..typename..") return "..typename.." is");
+ indent_right();
emit("variable tmp: "..typename..";");
+ indent_left();
emit("begin");
+ indent_right();
for i=1,table.getn(g_portlist) do
local port = g_portlist[i];
@@ -137,8 +162,11 @@ function cgen_vhdl_package()
end
end
emit("return tmp;");
+ indent_left();
emit("end function;");
+ emit("");
+ indent_left();
emit("end package body;");
end
@@ -189,6 +217,7 @@ function cgen_vhdl_port_struct(direction)
emit(line);
end
emit(");");
+ indent_left();
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0004-added-missing-function-for-type-un-signed.patch deleted 100644 → 0
View file @ 0ca74d29
From c68298349ed1c3ede781af609a073911160160bb Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 19:13:11 +0200
Subject: [PATCH 4/7] added missing function for type (un)signed
---
cgen_vhdl.lua | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/cgen_vhdl.lua b/cgen_vhdl.lua
index 1bafa9b..6d50d1b 100644
--- a/cgen_vhdl.lua
+++ b/cgen_vhdl.lua
@@ -12,6 +12,7 @@
-- Modifications:
-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
-- * better indent for VHDL package
+-- * added missing function for type (un)signed
--------------------------------------------------------------------------------
-- conversion table between VHDL data types and wbgen2 internal data types
@@ -94,9 +95,11 @@ function cgen_vhdl_package()
local typename = "t_"..periph.hdl_prefix.."_in_registers";
- emit("function \"or\" (left, right: "..typename..") return "..typename..";");
emit("function f_x_to_zero (x:std_logic) return std_logic;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector;");
+ emit("function f_x_to_zero (x:signed) return signed;");
+ emit("function f_x_to_zero (x:unsigned) return unsigned;");
+ emit("function \"or\" (left, right: "..typename..") return "..typename..";");
emit("");
indent_left();
@@ -147,6 +150,22 @@ function cgen_vhdl_package()
emit("end function;");
emit("");
+ emit("function f_x_to_zero (x:signed) return signed is");
+ emit("begin");
+ indent_right();
+ emit("return signed(f_x_to_zero(std_logic_vector(x)));");
+ indent_left();
+ emit("end function;");
+ emit("");
+
+ emit("function f_x_to_zero (x:unsigned) return unsigned is");
+ emit("begin");
+ indent_right();
+ emit("return unsigned(f_x_to_zero(std_logic_vector(x)));");
+ indent_left();
+ emit("end function;");
+ emit("");
+
emit("function \"or\" (left, right: "..typename..") return "..typename.." is");
indent_right();
emit("variable tmp: "..typename..";");
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0005-commented-out-debug-output.patch deleted 100644 → 0
View file @ 0ca74d29
From 8223570a84001abf102936a46d975ccc8d2c469d Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 19:21:19 +0200
Subject: [PATCH 5/7] commented out debug output
---
wbgen_common.lua | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/wbgen_common.lua b/wbgen_common.lua
index 68e0190..9a34596 100644
--- a/wbgen_common.lua
+++ b/wbgen_common.lua
@@ -200,9 +200,9 @@ function align(field, offset)
newofs = a * math.floor((offset + a - 1) / a);
end
--- calculate the aligned offset
+ -- calculate the aligned offset
- print("Align ", field.name, field.align, offset, newofs);
+ -- print("Align ", field.name, field.align, offset, newofs);
return newofs;
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0006-prettier-VHDL-output-rddata_reg-31-downto-8-others-X.patch deleted 100644 → 0
View file @ 0ca74d29
From 7e2536fa48aa59724b76c3e50776f864746a6297 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 20:15:19 +0200
Subject: [PATCH 6/7] prettier VHDL output ("rddata_reg(31 downto 8) <= (others
=> 'X');" instead of 24 individual lines)
---
wbgen_regbank.lua | 87 ++++++++++++++++++++++++++++++++++++++-----------------
1 file changed, 60 insertions(+), 27 deletions(-)
diff --git a/wbgen_regbank.lua b/wbgen_regbank.lua
index 230d441..96eea9d 100644
--- a/wbgen_regbank.lua
+++ b/wbgen_regbank.lua
@@ -5,6 +5,14 @@
-- CERN BE-Co-HT
-- LICENSED UNDER GPL v2
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * prettier VHDL output
+-- "rddata_reg(31 downto 8) <= (others => 'X');" instead of
+-- 24 individual lines
+--------------------------------------------------------------------------------
+
function gen_hdl_field_prefix(field, reg)
local field_count;
@@ -650,34 +658,59 @@ end
-- generates code which loads data unused bits of data output register with Xs
function fill_unused_bits(target, reg)
- local t={};
- local code={};
- local all_wo = true;
-
- foreach_subfield(reg, function(field, reg)
- if(field.type == SLV or field.type == SIGNED or field.type == UNSIGNED or field.type == CONSTANT) then
- for i=field.offset, (field.offset+field.size-1) do t[i] = 1; end
- elseif(field.type == BIT or field.type == MONOSTABLE) then
- t[field.offset] = 1;
- end
-
- if(field.access_bus ~= WRITE_ONLY) then all_wo = false; end
- end);
-
- if(all_wo) then
- for i = 0, DATA_BUS_WIDTH-1 do
- table_join(code, { va(vi(target, i), vundefined()); });
- end
- return code;
- end
+ local t={};
+ local code={};
+ local all_wo = true;
+
+ foreach_subfield(
+ reg,
+ function(field, reg)
+ if(field.type == SLV or field.type == SIGNED or field.type == UNSIGNED or field.type == CONSTANT) then
+ for i=field.offset, (field.offset+field.size-1) do
+ t[i] = 1;
+ end
+ elseif(field.type == BIT or field.type == MONOSTABLE) then
+ t[field.offset] = 1;
+ end
+
+ if(field.access_bus ~= WRITE_ONLY) then
+ all_wo = false;
+ end
+ end
+ );
+
+ function fill_unused_bits_range(target, from, to)
+ if(from == to) then
+ table_join(code, { va(vi(target, from), vundefined()); });
+ else
+ table_join(code, { va(vi(target, to, from), vothers('X')); });
+ end
+ end
- for i = 0, DATA_BUS_WIDTH-1 do
- if(t[i] == nil) then
- table_join(code, { va(vi(target, i), vundefined()); });
- end
- end
-
- return code;
+ if(all_wo) then
+ fill_unused_bits_range(target, 0, DATA_BUS_WIDTH-1);
+ return code;
+ end
+
+ range_start = nil;
+ for i = 0, DATA_BUS_WIDTH-1 do
+ if(t[i] == nil) then
+ if(range_start == nil) then
+ range_start = i;
+ end
+ else -- t[i] ~= nil
+ if(range_start ~= nil) then
+ fill_unused_bits_range(target, range_start, i-1);
+ range_start = nil;
+ end
+ end
+ end
+ if(range_start ~= nil) then
+ fill_unused_bits_range(target, range_start, DATA_BUS_WIDTH-1);
+ range_start = nil;
+ end
+
+ return code;
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0007-added-functions-print_table-and-table_size-disable-c.patch deleted 100644 → 0
View file @ 0ca74d29
From 91af40398c34cc8c2afe9869404199116b401470 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Thu, 25 Aug 2016 14:32:16 +0200
Subject: [PATCH 7/7] added functions print_table and table_size; disable
comment output for no extra code (field.extra_code seems to always be a
table)
---
target_pipelined_wb.lua | 10 ++++++++--
wbgen_common.lua | 28 ++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/target_pipelined_wb.lua b/target_pipelined_wb.lua
index 2dcabfa..899a7f1 100644
--- a/target_pipelined_wb.lua
+++ b/target_pipelined_wb.lua
@@ -1,5 +1,11 @@
-- -*- Mode: LUA; tab-width: 2 -*-
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-25: by Jan Pospisil (j.pospisil@cern.ch)
+-- * disable comment output for no extra code (field.extra_code seems
+-- to always be a table)
+--------------------------------------------------------------------------------
MAX_ACK_LENGTH = 10;
@@ -282,9 +288,9 @@ function gen_bus_logic_pipelined_wb(mode)
foreach_subfield(reg,
function(field, reg)
- if (field.extra_code ~= nil) then
+ if (field.extra_code ~= nil and table_size(field.extra_code) > 0) then
table_join(ex_code, {vcomment(field.name); field.extra_code});
- end
+ end
end );
if(reg.optional == nil) then
diff --git a/wbgen_common.lua b/wbgen_common.lua
index 9a34596..e8f320f 100644
--- a/wbgen_common.lua
+++ b/wbgen_common.lua
@@ -1,5 +1,11 @@
-- -*- Mode: LUA; tab-width: 2 -*-
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-25: by Jan Pospisil (j.pospisil@cern.ch)
+-- * added functions print_table and table_size
+--------------------------------------------------------------------------------
+
-- some constants --
-- DEBUG MACROS
@@ -558,3 +564,25 @@ function deepcopy(object)
end
return _copy(object)
end
+
+function print_table(t, level)
+ level = level or 0
+ local indent = ""
+ for i = 1,level do indent=indent.." "; end
+ for k,v in pairs(t) do
+ if (type(v)=="table") then
+ print(indent..k..", "..type(v)..", "..table_size(v));
+ print_table(v, level+1);
+ else
+ print(indent..k..", "..type(v)..", "..tostring(v));
+ end
+ end
+end
+
+function table_size(t)
+ local size = 0
+ for k,v in pairs(t) do
+ size = size + 1
+ end
+ return size
+end
--
2.8.1.windows.1
wr-cores @ 63d6e85c
Subproject commit 63d6e85c292e57360fe106acfd08de66d3c0acb7
hdl/svec/rtl/HeartBeat.vhd deleted 100644 → 0
View file @ 0ca74d29
-------------------------------------------------------------------------------
-- Title : Heart beat generator
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : HeartBeat.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-28
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Generates "glowing" signal, intended for LED signalization.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HeartBeat is
generic (
g_ClkFrequency: positive -- input clock frequency in Hz
);
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
HeartBeat_o: out std_logic := '0'
);
end entity;
architecture syn of HeartBeat is
--! computes least possible width of the vector to store value X
-- http://stackoverflow.com/a/12751341/615627
function f_log2(x: natural) return natural is
variable i: natural;
begin
i := 0;
while (2**i < x) loop
i := i + 1;
end loop;
return i;
end function;
function f_min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function f_max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
constant c_ClkFreqWidth: positive := f_log2(g_ClkFrequency);
constant c_PwmWidth: positive := f_max(f_min(c_ClkFreqWidth, 12), 4);
constant c_DividerWidth: natural := c_ClkFreqWidth - c_PwmWidth;
constant c_DividerLimit: natural := g_ClkFrequency / (2**c_PwmWidth);
signal PwmCountDown: std_logic := '0';
signal UpdatePwmValue, PwmCounterOverflow: std_logic;
signal PwmCounter_b, PwmValue_b, PwmValue_bd: signed(c_PwmWidth-1 downto 0) := (others => '0');
begin
gNeedDivider: if c_DividerWidth > 0 generate
cDivider: entity work.Counter(syn)
generic map (
g_Width => c_DividerWidth,
g_Limit => c_DividerLimit
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Enable_i => '1',
Set_i => '0',
SetValue_ib => (others => '0'),
Overflow_o => UpdatePwmValue,
Value_ob => open
);
end generate;
gDoesntNeedDivider: if c_DividerWidth = 0 generate
UpdatePwmValue <= '1';
end generate;
pPwmValue: process (Clk_ik) begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
PwmValue_b <= (others => '0');
PwmCountDown <= '0';
elsif UpdatePwmValue = '1' then
if PwmCountDown = '1' then
if PwmValue_b = to_signed(1, c_PwmWidth) then
PwmCountDown <= '0';
PwmValue_b <= PwmValue_b + 1;
else
PwmValue_b <= PwmValue_b - 1;
end if;
else
if PwmValue_b = to_signed(-1, c_PwmWidth) then
PwmCountDown <= '1';
PwmValue_b <= PwmValue_b - 1;
else
PwmValue_b <= PwmValue_b + 1;
end if;
end if;
end if;
end if;
end process;
cPwmCounter: entity work.Counter(syn)
generic map (
g_Width => c_PwmWidth
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Enable_i => '1',
Set_i => '0',
SetValue_ib => (others => '0'),
Overflow_o => PwmCounterOverflow,
signed(Value_ob) => PwmCounter_b
);
pPwmValueReg: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if PwmCounterOverflow = '1' then
PwmValue_bd <= PwmValue_b;
end if;
end if;
end process;
pHearBeat: process (Clk_ik) begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
HeartBeat_o <= '0';
else
if PwmCounter_b = 0 then
HeartBeat_o <= '1';
end if;
if PwmCounter_b = PwmValue_bd then
HeartBeat_o <= '0';
end if;
end if;
end if;
end process;
end architecture;
hdl/svec/rtl/HeartBeat_tb.vhd deleted 100644 → 0
View file @ 0ca74d29
-------------------------------------------------------------------------------
-- Title : Testbench for HeartBeat.vhd
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : HeartBeat_tb.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-28
-- Last update: 2016-08-24
-- Standard : VHDL2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HeartBeat_tb is
end entity;
architecture testbench of HeartBeat_tb is
constant c_ClkFrequency: positive := 300_000;
constant c_ClkPeriod: time := (1 sec)/real(c_ClkFrequency);
procedure f_Tick(ticks: in natural) is begin
wait for ticks * c_ClkPeriod;
end procedure;
signal Clk_ik, Reset_ir, HeartBeat_o: std_logic;
signal HeartBeatPwmValue: time := 0 ns;
begin
cDUT: entity work.HeartBeat(syn)
generic map (
g_ClkFrequency => c_ClkFrequency
)
port map (
Clk_ik,
Reset_ir,
HeartBeat_o
);
pClk: process is begin
Clk_ik <= '0';
wait for c_ClkPeriod/2;
Clk_ik <= '1';
wait for c_ClkPeriod/2;
end process;
pTest: process is begin
Reset_ir <= '1';
f_Tick(5);
Reset_ir <= '0';
f_Tick(1e6);
assert false report "NONE. End of simulation." severity failure;
wait;
end process pTest;
pRC: process (HeartBeat_o) is
variable LastOn: time := 0 ns;
begin
if rising_edge(HeartBeat_o) then
LastOn := now;
else
HeartBeatPwmValue <= now - LastOn;
end if;
end process;
end architecture;
hdl/svec/rtl/SvecTopFfpg.vhd deleted 100644 → 0
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hdl/svec/rtl/carrier_csr.vhd deleted 100644 → 0
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : 12/19/16 17:04:37
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(10 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC 1 presence' in reg: 'Status'
carrier_csr_stat_fmc0_pres_i : in std_logic;
-- Port for BIT field: 'FMC 2 presence' in reg: 'Status'
carrier_csr_stat_fmc1_pres_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 4 calibration status' in reg: 'Status'
carrier_csr_stat_ddr0_cal_done_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 5 calibration status' in reg: 'Status'
carrier_csr_stat_ddr1_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'NOT_IMPLEMENTED: Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
-- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 5) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_csr_stat_fmc0_pres_i;
rddata_reg(1) <= carrier_csr_stat_fmc1_pres_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
rddata_reg(31 downto 5) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc1_n_load_o <= '1';
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(1) <= carrier_csr_rst_fmc1_n_i;
rddata_reg(31 downto 2) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- NOT_IMPLEMENTED: Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o <= wrdata_reg(1);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (ack_in_progress or (wb_stb_i and wb_cyc_i));
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/svec/sim/testbench/ConfigSvec.svh deleted 100644 → 0
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`ifndef CONFIG_SVEC_SVH
`define CONFIG_SVEC_SVH
`define WB_SVEC_VME_ADDRESS 0
`define WB_FFPG_BASE (`WB_SVEC_VME_ADDRESS + 'h2_0000)
`define WB_FFPG_SPI_BASE (`WB_FFPG_BASE + 'h1000)
`define WB_FFPG_OW_BASE (`WB_FFPG_BASE + 'h1100)
`define WB_FFPG_CSR_BASE (`WB_FFPG_BASE + 'h1_0000)
`define WB_FFPG_SPI_REG(REG_ADDRESS) (`WB_FFPG_SPI_BASE + REG_ADDRESS)
`define WB_FFPG_OW_REG(REG_ADDRESS) (`WB_FFPG_OW_BASE + REG_ADDRESS)
`define WB_FFPG_CSR_REG(REG_ADDRESS) (`WB_FFPG_CSR_BASE + REG_ADDRESS)
// SPI regs.
`define SPI_TX_RX_0 'h00
`define SPI_TX_RX_1 'h04
`define SPI_TX_RX_2 'h08
`define SPI_TX_RX_3 'h0c
`define SPI_CTRL 'h10
`define SPI_DIVIDER 'h14
`define SPI_SS 'h18
`endif //CONFIG_SVEC_SVH
hdl/svec/sim/testbench/SvecTopFfpgWrapper.vhd deleted 100644 → 0
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hdl/svec/sim/testbench/Testbench.sv deleted 100644 → 0
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//-----------------------------------------------------------------------------
// Title : Testbench for implementation on SVEC carrier card
// Project : FMC DEL 1ns 2cha (FFPG)
// URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
//-----------------------------------------------------------------------------
// File : Testbench.sv
// Author(s) : Jan Pospisil <j.pospisil@cern.ch>
// Company : CERN (BE-BI-QP)
// Created : 2016-08-03
// Last update: 2016-08-24
// Standard : SystemVerilog
//-----------------------------------------------------------------------------
// Description:
//-----------------------------------------------------------------------------
// Copyright (c) 2016 CERN (BE-BI-QP)
//-----------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//-----------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author
// 2016-08-24 1.0 Jan Pospisil
//-----------------------------------------------------------------------------
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "fmc.svh"
`include "../../../ffpg/sim/testbench/ffpg_csr.svh"
`include "carrier_csr.svh"
`include "ConfigSvec.svh"
module Testbench;
reg Reset_inr = 0;
reg Clk20_ik = 0;
reg ClkRf_k = 0;
reg Trigger = 0;
int BunchCounter = 0;
always #25ns Clk20_ik <= ~Clk20_ik;
always #5ns ClkRf_k <= ~ClkRf_k; // 200 MHz
always_ff @(posedge ClkRf_k) begin
if (BunchCounter == 17820) begin
BunchCounter <= 0;
Trigger <= 1;
end else begin
BunchCounter <= BunchCounter + 1;
Trigger <= 0;
end
end
initial begin
#10us; // for PLL lock and reset settle
repeat(20) @(posedge Clk20_ik);
Reset_inr = 1;
end
IVME64X VME(Reset_inr);
`DECLARE_VME_BUFFERS(VME.slave);
`DECLARE_FMC(0);
`DECLARE_FMC(1);
logic [1:0] FpLedsLineEnable_ob2;
logic [1:0] FpLedsLine_ob2;
logic [3:0] FpLedsColumn_ob4;
wire CarrierScl_io;
wire CarrierSda_io;
wire CarrierOneWire_io;
pullup(CarrierScl_io);
pullup(CarrierSda_io);
CBusAccessor_VME64x acc;
SvecTopFfpgWrapper cDut (
.Clk20_ik(Clk20_ik),
.Reset_inr(Reset_inr),
.Pll20DacDin_o(),
.Pll20DacSclk_o(),
.Pll20DacSync_on(),
.Pll25DacDin_o(),
.Pll25DacSclk_o(),
.Pll25DacSync_on(),
.FpLedsLineEnable_ob2(FpLedsLineEnable_ob2),
.FpLedsLine_ob2(FpLedsLine_ob2),
.FpLedsColumn_ob4(FpLedsColumn_ob4),
.CarrierScl_io(CarrierScl_io),
.CarrierSda_io(CarrierSda_io),
.PcbRev_i(5'b00001),
.CarrierOneWire_io(CarrierOneWire_io),
`WIRE_FMC(0)
`WIRE_FMC(1)
`WIRE_VME_PINS(8) // slot number in parameter // don't change that magic 8 - it's hardcoded somewhere else
);
assign Fmc0Present_in = 1;
assign Fmc0ClkIn0P_ik = ClkRf_k;
assign Fmc0ClkIn0N_ik = ~Fmc0ClkIn0P_ik;
assign Fmc0TriggerP_i = Trigger;
assign Fmc0TriggerN_i = ~Fmc0TriggerP_i;
assign Fmc0SpiAd9512Miso_i = Fmc0SpiAd9512Mosi_o; // loopback
assign Fmc1Present_in = 1;
assign Fmc1ClkIn0P_ik = ClkRf_k;
assign Fmc1ClkIn0N_ik = ~Fmc1ClkIn0P_ik;
assign Fmc1TriggerP_i = Trigger;
assign Fmc1TriggerN_i = ~Fmc1TriggerP_i;
assign Fmc1SpiAd9512Miso_i = Fmc1SpiAd9512Mosi_o; // loopback
task automatic init_vme64x_core;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3); // maybe here?
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask
task automatic WbWrite(uint32_t address, uint32_t data, string label = "");
uint64_t data64 = data;
if (label != "")
$display(label);
acc.write(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data);
#1us; // not to issue commands too fast, to better simulate real behaviour
endtask
task automatic WbRead(uint32_t address, output uint32_t data, input string label = "");
uint64_t data64;
if (label != "")
$display(label);
acc.read(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data64[31:0]);
data = data64[31:0];
#1us; // not to issue commands too fast, to better simulate real behaviour
endtask
task automatic TestSdb;
uint64_t d;
uint32_t base;
uint32_t address;
int i;
base = `WB_SVEC_VME_ADDRESS;
$display("Carrier SDB:");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
end
base = `WB_FFPG_BASE + 64*0;
$display("FFPG SDB:");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
end
endtask
task automatic TestFfpgCsr;
uint64_t d;
uint32_t base;
uint32_t address;
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS);
$display("FFPG Status reg.:");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL);
$display("Control reg. write:");
d = 4;
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS);
$display("FFPG Status reg.:");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
endtask
task automatic TestReal;
`include "z:/FFPG/wb_trace.svh"
// #1ms;
// WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_DEBUG), dataOut, "Debug");
endtask
task automatic TestAd9512Sync;
uint32_t data;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h200);
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
#200us;
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
endtask
task automatic WaitUntilReady;
uint32_t data;
do
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS), data);
while (data & 'b1111);
endtask
initial begin
acc = new(VME);
#10us; // for PLL lock and reset settle
#20us;
init_vme64x_core;
WaitUntilReady;
#5us
// TestSdb;
// TestFfpgCsr;
TestReal;
// TestAd9512Sync;
// TestAd9512Sync;
// uint64_t blt_addr[];
// uint64_t blt_data[];
// $display("Write data to DDR in BLT\n");
// blt_addr = {'h3000};
// blt_data = {'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8 ,'h9, 'hA};
// acc.writem(blt_addr, blt_data, A32|BLT|D32, result);
// $display("Read data from DDR in BLT");
// blt_data = {};
// acc.readm(blt_addr, blt_data, A32|BLT|D32, result);
// for(i=0; i<10; i++) begin
// $display("Data %d: 0x%x\n", i, blt_data[i]);
// end
$stop;
end
endmodule
hdl/svec/sim/testbench/carrier_csr.svh deleted 100644 → 0
View file @ 0ca74d29
`define ADDR_CARRIER_CSR_CARRIER 4'h0
`define CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define CARRIER_CSR_CARRIER_PCB_REV 32'h0000001f
`define CARRIER_CSR_CARRIER_RESERVED_OFFSET 5
`define CARRIER_CSR_CARRIER_RESERVED 32'h0000ffe0
`define CARRIER_CSR_CARRIER_TYPE_OFFSET 16
`define CARRIER_CSR_CARRIER_TYPE 32'hffff0000
`define ADDR_CARRIER_CSR_STAT 4'h4
`define CARRIER_CSR_STAT_FMC0_PRES_OFFSET 0
`define CARRIER_CSR_STAT_FMC0_PRES 32'h00000001
`define CARRIER_CSR_STAT_FMC1_PRES_OFFSET 1
`define CARRIER_CSR_STAT_FMC1_PRES 32'h00000002
`define CARRIER_CSR_STAT_SYS_PLL_LCK_OFFSET 2
`define CARRIER_CSR_STAT_SYS_PLL_LCK 32'h00000004
`define CARRIER_CSR_STAT_DDR0_CAL_DONE_OFFSET 3
`define CARRIER_CSR_STAT_DDR0_CAL_DONE 32'h00000008
`define CARRIER_CSR_STAT_DDR1_CAL_DONE_OFFSET 4
`define CARRIER_CSR_STAT_DDR1_CAL_DONE 32'h00000010
`define ADDR_CARRIER_CSR_CTRL 4'h8
`define CARRIER_CSR_CTRL_FP_LEDS_MAN_OFFSET 0
`define CARRIER_CSR_CTRL_FP_LEDS_MAN 32'h0000ffff
`define ADDR_CARRIER_CSR_RST 4'hc
`define CARRIER_CSR_RST_FMC0_N_OFFSET 0
`define CARRIER_CSR_RST_FMC0_N 32'h00000001
`define CARRIER_CSR_RST_FMC1_N_OFFSET 1
`define CARRIER_CSR_RST_FMC1_N 32'h00000002
hdl/svec/sim/testbench/components/sn74vmeh22501.v deleted 100644 → 0
View file @ 0ca74d29
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/components/sn74vmeh22501.v
`timescale 1ns/1ns
module sn74vmeh22501 (
input oeab1,
oeby1_n,
a1,
output y1,
inout b1,
input oeab2,
oeby2_n,
a2,
output y2,
inout b2,
input oe_n,
input dir,
clkab,
le,
clkba,
inout [1:8] a3,
inout [1:8] b3);
assign b1 = oeab1 ? a1 : 1'bz;
assign y1 = oeby1_n ? 1'bz : b1;
assign b2 = oeab2 ? a2 : 1'bz;
assign y2 = oeby2_n ? 1'bz : b2;
reg [1:8] b3LFF;
always @(posedge clkab) if (~le) b3LFF <= #1 a3;
always @* if (le) b3LFF = a3;
assign b3 = (~oe_n && dir) ? b3LFF : 8'hz;
reg [1:8] a3LFF;
always @(posedge clkba) if (~le) a3LFF <= #1 b3;
always @* if (le) a3LFF = b3;
assign a3 = (~oe_n && ~dir) ? a3LFF : 8'hz;
endmodule
hdl/svec/sim/testbench/fmc.svh deleted 100644 → 0
View file @ 0ca74d29
`define DECLARE_FMC(__nb) \
logic Fmc``__nb``ClkIn0P_ik; \
logic Fmc``__nb``ClkIn0N_ik; \
logic Fmc``__nb``TriggerDac_o_FrameSynchronization_n; \
logic Fmc``__nb``TriggerDac_o_SerialClock; \
logic Fmc``__nb``TriggerDac_o_SerialData; \
logic Fmc``__nb``VcxoDac_o_FrameSynchronization_n; \
logic Fmc``__nb``VcxoDac_o_SerialClock; \
logic Fmc``__nb``VcxoDac_o_SerialData; \
logic Fmc``__nb``Ch1OutputEnable_o; \
logic Fmc``__nb``Ch2OutputEnable_o; \
logic Fmc``__nb``Ch1OutCal_i; \
logic Fmc``__nb``Ch2OutCal_i; \
logic [9:0] Fmc``__nb``DelayValue_ob; \
logic Fmc``__nb``Ch1SetLe_on; \
logic Fmc``__nb``Ch1ResLe_on; \
logic Fmc``__nb``Ch2SetLe_on; \
logic Fmc``__nb``Ch2ResLe_on; \
logic Fmc``__nb``Ch1SetP_o; \
logic Fmc``__nb``Ch1SetN_o; \
logic Fmc``__nb``Ch1ResP_o; \
logic Fmc``__nb``Ch1ResN_o; \
logic Fmc``__nb``Ch2SetP_o; \
logic Fmc``__nb``Ch2SetN_o; \
logic Fmc``__nb``Ch2ResP_o; \
logic Fmc``__nb``Ch2ResN_o; \
logic Fmc``__nb``TriggerP_i; \
logic Fmc``__nb``TriggerN_i; \
logic Fmc``__nb``SpiAd9512Sclk_o; \
logic Fmc``__nb``SpiAd9512Mosi_o; \
logic Fmc``__nb``SpiAd9512Miso_i; \
logic Fmc``__nb``SpiAd9512Cs_on; \
logic Fmc``__nb``Ad9512Func_o; \
logic Fmc``__nb``Clk2Sel_o; \
logic Fmc``__nb``ClkOutP_ok; \
logic Fmc``__nb``ClkOutN_ok; \
wire Fmc``__nb``Onewire_io; \
logic [4:1] Fmc``__nb``Led_ob; \
logic Fmc``__nb``Present_in;
`define WIRE_FMC(__nb) \
.Fmc``__nb``ClkIn0P_ik(Fmc``__nb``ClkIn0P_ik), \
.Fmc``__nb``ClkIn0N_ik(Fmc``__nb``ClkIn0N_ik), \
.Fmc``__nb``TriggerDac_o_FrameSynchronization_n(Fmc``__nb``TriggerDac_o_FrameSynchronization_n), \
.Fmc``__nb``TriggerDac_o_SerialClock(Fmc``__nb``TriggerDac_o_SerialClock), \
.Fmc``__nb``TriggerDac_o_SerialData(Fmc``__nb``TriggerDac_o_SerialData), \
.Fmc``__nb``VcxoDac_o_FrameSynchronization_n(Fmc``__nb``VcxoDac_o_FrameSynchronization_n), \
.Fmc``__nb``VcxoDac_o_SerialClock(Fmc``__nb``VcxoDac_o_SerialClock), \
.Fmc``__nb``VcxoDac_o_SerialData(Fmc``__nb``VcxoDac_o_SerialData), \
.Fmc``__nb``Ch1OutputEnable_o(Fmc``__nb``Ch1OutputEnable_o), \
.Fmc``__nb``Ch2OutputEnable_o(Fmc``__nb``Ch2OutputEnable_o), \
.Fmc``__nb``Ch1OutCal_i(Fmc``__nb``Ch1OutCal_i), \
.Fmc``__nb``Ch2OutCal_i(Fmc``__nb``Ch2OutCal_i), \
.Fmc``__nb``DelayValue_ob(Fmc``__nb``DelayValue_ob), \
.Fmc``__nb``Ch1SetLe_on(Fmc``__nb``Ch1SetLe_on), \
.Fmc``__nb``Ch1ResLe_on(Fmc``__nb``Ch1ResLe_on), \
.Fmc``__nb``Ch2SetLe_on(Fmc``__nb``Ch2SetLe_on), \
.Fmc``__nb``Ch2ResLe_on(Fmc``__nb``Ch2ResLe_on), \
.Fmc``__nb``Ch1SetP_o(Fmc``__nb``Ch1SetP_o), \
.Fmc``__nb``Ch1SetN_o(Fmc``__nb``Ch1SetN_o), \
.Fmc``__nb``Ch1ResP_o(Fmc``__nb``Ch1ResP_o), \
.Fmc``__nb``Ch1ResN_o(Fmc``__nb``Ch1ResN_o), \
.Fmc``__nb``Ch2SetP_o(Fmc``__nb``Ch2SetP_o), \
.Fmc``__nb``Ch2SetN_o(Fmc``__nb``Ch2SetN_o), \
.Fmc``__nb``Ch2ResP_o(Fmc``__nb``Ch2ResP_o), \
.Fmc``__nb``Ch2ResN_o(Fmc``__nb``Ch2ResN_o), \
.Fmc``__nb``TriggerP_i(Fmc``__nb``TriggerP_i), \
.Fmc``__nb``TriggerN_i(Fmc``__nb``TriggerN_i), \
.Fmc``__nb``SpiAd9512Sclk_o(Fmc``__nb``SpiAd9512Sclk_o), \
.Fmc``__nb``SpiAd9512Mosi_o(Fmc``__nb``SpiAd9512Mosi_o), \
.Fmc``__nb``SpiAd9512Miso_i(Fmc``__nb``SpiAd9512Miso_i), \
.Fmc``__nb``SpiAd9512Cs_on(Fmc``__nb``SpiAd9512Cs_on), \
.Fmc``__nb``Ad9512Func_o(Fmc``__nb``Ad9512Func_o), \
.Fmc``__nb``Clk2Sel_o(Fmc``__nb``Clk2Sel_o), \
.Fmc``__nb``ClkOutP_ok(Fmc``__nb``ClkOutP_ok), \
.Fmc``__nb``ClkOutN_ok(Fmc``__nb``ClkOutN_ok), \
.Fmc``__nb``Onewire_io(Fmc``__nb``Onewire_io), \
.Fmc``__nb``Led_ob(Fmc``__nb``Led_ob), \
.Fmc``__nb``Present_in(Fmc``__nb``Present_in),
hdl/svec/sim/testbench/make deleted 100644 → 0
View file @ 0ca74d29
# clean working space and compile all necessary files
# I want the HDLmake to run under Windows!
vlib work
vdel -lib work -all
vlib work
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_dpssram.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_eic.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_fifo_async.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_fifo_sync.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/PulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/PulseGeneratorTime.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Counter.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/CounterLength.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ShiftRegister.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ResetSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Delay.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/EdgeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ChangeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Reg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/RegSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/SlowToggle.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FrequencySense.vhd
vlog -reportprogress 300 -work work ../../../ffpg/rtl/SpiMasterWb.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Ad9512Control.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgPkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ffpg_csr_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ffpg_csr.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/WbSlaveWrapper.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Ad9512Syncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgSlave.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgCore.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/carrier_csr.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/HeartBeat.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/SvecTopFfpg.vhd
vcom -2008 -reportprogress 300 -work work SvecTopFfpgWrapper.vhd
vlog -reportprogress 300 -work work Testbench.sv +incdir+../../../ip_cores/general-cores/sim
hdl/svec/sim/testbench/post_map deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/map/SvecTopFfpg_map.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/map/SvecTopFfpg_map.sdf work.Testbench
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_par deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/par/SvecTopFfpg_timesim.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/par/SvecTopFfpg_timesim.sdf work.Testbench
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_syn deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/synthesis/SvecTopFfpg_synthesis.vhd
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_tra deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/translate/SvecTopFfpg_translate.vhd
do res
\ No newline at end of file
hdl/svec/sim/testbench/re deleted 100644 → 0
View file @ 0ca74d29
# recompile and restart with new random seed
#do make
vlog -reportprogress 300 -work work Testbench.sv +incdir+../../../ip_cores/general-cores/sim
do res
hdl/svec/sim/testbench/res deleted 100644 → 0
View file @ 0ca74d29
# restart simulation with new random seed
restart -force -sv_seed random
do run
hdl/svec/sim/testbench/run deleted 100644 → 0
View file @ 0ca74d29
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
run 0 ns
set NumericStdNoWarnings 0
set StdArithNoWarnings 0
run -all
\ No newline at end of file
hdl/svec/sim/testbench/sim deleted 100644 → 0
View file @ 0ca74d29
# start simulation, set waveform, run simulation
vsim -voptargs=+acc work.Testbench
add wave -group DUT sim:/Testbench/cDut/cSvecTopFfpg/*
# add wave -group {Xbar SVEC} sim:/Testbench/cDut/cSvecTopFfpg/cWbSdbCrossbar/*
# add wave -group {Xbar FFPGCore} sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cWbSdbCrossbar/*
add wave -group FFPGCore sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/*
add wave -group FFPGSlave sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/*
# add wave -group FFPGSlave -group WbSlave sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cWbSlaveWrapper/*
# add wave -group FFPGSlave -group DacsController sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDacsController/*
# add wave -group FFPGSlave -group DelayController -r sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayController/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group Fsm sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cFsm/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group BitCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cBitCounter/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group StreamCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cStreamCounter/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group ShiftRegisterSet sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cShiftRegisterSet/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group ShiftRegisterReset sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cShiftRegisterReset/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group Fsm sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cFsm/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group BitCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cBitCounter/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group StreamCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cStreamCounter/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group ShiftRegisterSet sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cShiftRegisterSet/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group ShiftRegisterReset sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cShiftRegisterReset/*
configure wave -namecolwidth 271
configure wave -valuecolwidth 100
configure wave -signalnamewidth 1
sv_reseed random
do run
wave zoomfull
hdl/svec/sim/testbench/svec_vme_buffers.svh deleted 100644 → 0
View file @ 0ca74d29
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/svec_vme_buffers.svh
// modified by Jan Pospisil, j.pospisil@cern.ch, 2016, CERN BE-BI-QP
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
module bidir_buf(
a,
b,
dir, /* 0: a->b, 1: b->a */
oe_n );
parameter g_width = 1;
inout [g_width-1:0] a,b;
input dir, oe_n;
assign b = (!dir && !oe_n) ? a : 'bz;
assign a = (dir && !oe_n) ? b : 'bz;
endmodule // bidir_buf
module svec_vme_buffers (
output VME_AS_n_o,
output VME_RST_n_o,
output VME_WRITE_n_o,
output [5:0] VME_AM_o,
output [1:0] VME_DS_n_o,
output [5:0] VME_GA_o,
input VME_BERR_i,
input VME_DTACK_n_i,
input VME_RETRY_n_i,
input VME_RETRY_OE_i,
inout VME_LWORD_n_b,
inout [31:1] VME_ADDR_b,
inout [31:0] VME_DATA_b,
output VME_BBSY_n_o,
input [6:0] VME_IRQ_n_i,
output VME_IACKIN_n_o,
input VME_IACKOUT_n_i,
output VME_IACK_n_o,
input VME_DTACK_OE_i,
input VME_DATA_DIR_i,
input VME_DATA_OE_N_i,
input VME_ADDR_DIR_i,
input VME_ADDR_OE_N_i,
IVME64X.slave slave
);
pullup(slave.as_n);
pullup(slave.rst_n);
pullup(slave.irq_n[0]);
pullup(slave.irq_n[1]);
pullup(slave.irq_n[2]);
pullup(slave.irq_n[3]);
pullup(slave.irq_n[4]);
pullup(slave.irq_n[5]);
pullup(slave.irq_n[6]);
pullup(slave.iack_n);
pullup(slave.dtack_n);
pullup(slave.retry_n);
pullup(slave.ds_n[1]);
pullup(slave.ds_n[0]);
pullup(slave.lword_n);
pullup(slave.berr_n);
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
assign VME_RST_n_o = slave.rst_n;
assign VME_AS_n_o = slave.as_n;
assign VME_GA_o = slave.ga;
assign VME_WRITE_n_o = slave.write_n;
assign VME_AM_o = slave.am;
assign VME_DS_n_o = slave.ds_n;
assign VME_BBSY_n_o = slave.bbsy_n;
assign VME_IACKIN_n_o = slave.iackin_n;
assign VME_IACK_n_o = slave.iack_n;
bidir_buf #(1) b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(32) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
pulldown(VME_BERR_i);
pulldown(VME_ADDR_DIR_i);
pulldown(VME_ADDR_OE_N_i);
pulldown(VME_DATA_DIR_i);
pulldown(VME_DATA_OE_N_i);
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
endmodule
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_DS_n_o(VME_DS_n),\
.VME_GA_o(),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_o(),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
.slave(iface)\
);
function automatic bit[5:0] _gen_ga(int slot);
bit[4:0] slot_id = slot;
return {^slot_id, ~slot_id};
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VmeAs_n_i(VME_AS_n),\
.VmeSysreset_n_i(VME_RST_n),\
.VmeWrite_n_i(VME_WRITE_n),\
.VmeAm_i(VME_AM),\
.VmeDs_n_i(VME_DS_n),\
.VmeGa_i(_gen_ga(slot_id)),\
.VmeBerr_o(VME_BERR),\
.VmeDtack_n_o(VME_DTACK_n),\
.VmeRetry_n_o(VME_RETRY_n),\
.VmeRetry_oe_o(VME_RETRY_OE),\
.VmeLword_n_b(VME_LWORD_n),\
.VmeAddr_b(VME_ADDR),\
.VmeData_b(VME_DATA),\
.VmeIrq_n_o(VME_IRQ_n),\
.VmeIack_n_i(VME_IACK_n),\
.VmeIackin_n_i(VME_IACKIN_n),\
.VmeIackout_n_o(VME_IACKOUT_n),\
.VmeDtack_oe_o(VME_DTACK_OE),\
.VmeData_dir_o(VME_DATA_DIR),\
.VmeData_oe_n_o(VME_DATA_OE_N),\
.VmeAddr_dir_o(VME_ADDR_DIR),\
.VmeAddr_oe_n_o(VME_ADDR_OE_N)
hdl/svec/sim/testbench/vme64x_bfm.svh deleted 100644 → 0
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hdl/svec/wb_gen/Makefile deleted 100644 → 0
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WBGEN2=wbgen2
RTL=../rtl/
DOC=../../../doc/manual/svec/
SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
hdl/svec/wb_gen/carrier_csr.h deleted 100644 → 0
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/*
Register definitions for slave core: SVEC carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : 12/19/16 17:04:37
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 5
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 11)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC 1 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC0_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC 2 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC1_PRES WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 4 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR0_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 5 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1)
/* definitions for register: Control */
/* definitions for field: NOT_IMPLEMENTED: Front panel LED manual control in reg: Control */
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_MASK WBGEN2_GEN_MASK(0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_SHIFT 0
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#define CARRIER_CSR_PERIPH_PREFIX "carrier_csr"
#define CARRIER_CSR_PERIPH_NAME "SVEC carrier control and status registers"
#define CARRIER_CSR_PERIPH_DESC WBGEN2_DESC("Wishbone slave for control and status registers related to the SVEC FMC carrier")
#endif
hdl/svec/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ 0ca74d29
peripheral {
name = "SVEC carrier control and status registers";
description = "Wishbone slave for control and status registers related to the SVEC FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 11;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC 1 presence";
description = "0: FMC slot 1 is populated\n1: FMC slot 1 is not populated.";
prefix = "fmc0_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC 2 presence";
description = "0: FMC slot 2 is populated\n1: FMC slot 2 is not populated.";
prefix = "fmc1_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "NOT_IMPLEMENTED: DDR3 bank 4 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr0_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "NOT_IMPLEMENTED: DDR3 bank 5 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr1_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "NOT_IMPLEMENTED: Front panel LED manual control";
description = "NOT_IMPLEMENTED: Height front panel LED, two bits per LED.\n00 = OFF\n01 = Green\n10 = Red\n11 = Orange";
prefix = "fp_leds_man";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanines including the ddr interface and the time-tagging core.";
field {
name = "State of the FMC 1 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc0_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "State of the FMC 2 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc1_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
};
hdl/syn/svec/.gitignore 0 → 100644
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/svec/Manifest.py 0 → 100644
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top_ffpg"
syn_project = "svec_top_ffpg.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
"sourceid_{}_pkg.vhd".format(syn_top),
"svec_top_ffpg.ucf",
]
# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
# fetchto variable independent of where those Manifests reside in the filesystem.
# However, this needs to happen after the files section above, otherwise the two ucf files from the
# dependency will not be taken into account!!!
import os
fetchto = os.path.abspath(fetchto)
modules = {
"local" : [
"../../top/svec",
],
}
try:
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': syn_top})
except Exception as e:
print("Error: cannot generate source id file")
raise
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/svec/syn_extra_steps.tcl 0 → 100644
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/top/svec/Manifest.py 0 → 100644
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
files = [
"svec_top_ffpg.vhd",
"svec_top_ffpg_map.vhd",
]
modules = {
"local" : [
"../../ffpg/rtl",
"../../ip_cores/svec",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core",
"../../ip_cores/ddr3-sp6-core",
"../../ip_cores/wr-cores",
],
#"git" : [
# "https://ohwr.org/project/svec.git",
# "https://ohwr.org/project/general-cores.git",
# "https://ohwr.org/project/vme64x-core.git",
#],
}
hdl/top/svec/svec_top_ffpg.vhd 0 → 100644
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hdl/top/svec/svec_top_ffpg_map.cheby 0 → 100644
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: svec_top_ffpg_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ffpg0
description: FFPG core 0
address: 0x20000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ffpg1
description: FFPG core 1
address: 0x60000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/svec/svec_top_ffpg_map.vhd 0 → 100644
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