Commit 6f3130c2 authored by Jan Pospisil's avatar Jan Pospisil

fixed naming style; better test synchronization to the clock

parent 835859a9
......@@ -11,76 +11,76 @@ end entity;
architecture testbench of pulseGeneratorTime_tb is
constant CLK_FREQ: real := 200.0e6; -- in Hz
constant CLK_PERIOD: time := (1.0 sec)/CLK_FREQ;
constant c_ClkFrequency: positive := 200e6; -- in Hz
constant c_ClockPeriod: time := (1.0 sec)/c_ClkFrequency;
constant PULSE_MIN_WIDTH_TIME: time := 20 ns;
constant c_PulseMinWidthInTime: time := 1 ns;
signal clk, reset, signalIn, pulseOut: std_logic := '0';
signal lastPulseStart, lastPulseWidth: time := 0 ns;
signal Clk_k, Reset_r, SignalIn, PulseOut: std_logic := '0';
signal LastPulseStart, LastPulseWidth: time := 0 ns;
procedure tick(ticks: in natural) is begin
wait for ticks * CLK_PERIOD;
procedure f_tick(Ticks: in natural) is begin
wait for Ticks * c_ClockPeriod;
end procedure;
begin
cDUT: entity work.pulseGeneratorTime(syn)
i_Dut: entity work.pulseGeneratorTime(syn)
generic map (
CLK_FREQ => CLK_FREQ,
PULSE_MIN_WIDTH_TIME => PULSE_MIN_WIDTH_TIME
g_ClkFrequency => c_ClkFrequency,
g_PulseMinWidthInTime => c_PulseMinWidthInTime
)
port map (
clk,
reset,
signalIn,
pulseOut
Clk_ik => Clk_k,
Reset_ir => Reset_r,
Signal_i => SignalIn,
Pulse_o => PulseOut
);
pClk: process is begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
Clk_k <= '0';
wait for c_ClockPeriod/2;
Clk_k <= '1';
wait for c_ClockPeriod/2;
end process;
pPulseWidth: process (pulseOut) is
begin
if rising_edge(pulseOut) then
lastPulseStart <= now;
pPulseWidth: process (PulseOut) is begin
if rising_edge(PulseOut) then
LastPulseStart <= now;
else
lastPulseWidth <= now - lastPulseStart;
report "Last pulse width: " & time'image(now - lastPulseStart);
LastPulseWidth <= now - LastPulseStart;
report "Last pulse width: " & time'image(now - LastPulseStart);
end if;
end process;
pTest: process is
variable L: line;
begin
pTest: process is begin
-- init wait
tick(2);
f_tick(2);
-- try single output
signalIn <= '1';
tick(1);
signalIn <= '0';
wait on lastPulseWidth;
assert lastPulseWidth >= PULSE_MIN_WIDTH_TIME
wait until Clk_k = '0';
SignalIn <= '1';
f_tick(1);
SignalIn <= '0';
wait on LastPulseWidth;
assert LastPulseWidth >= c_PulseMinWidthInTime
report "Pulse is too short! (1)"
severity failure;
-- try multiple inputs
signalIn <= '1';
tick(1);
signalIn <= '0';
wait for PULSE_MIN_WIDTH_TIME/2;
signalIn <= '1';
tick(1);
signalIn <= '0';
wait on lastPulseWidth;
assert lastPulseWidth >= PULSE_MIN_WIDTH_TIME
wait until Clk_k = '0';
SignalIn <= '1';
f_tick(1);
SignalIn <= '0';
wait for c_PulseMinWidthInTime/2;
wait until Clk_k = '0';
SignalIn <= '1';
f_tick(1);
SignalIn <= '0';
wait on LastPulseWidth;
assert LastPulseWidth >= c_PulseMinWidthInTime
report "Pulse is too short! (1)"
severity failure;
assert false report "NONE. End of simulation." severity failure;
wait;
end process;
end architecture;
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