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FMC DEL 1ns 2cha
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FMC DEL 1ns 2cha
Commits
6f3130c2
Commit
6f3130c2
authored
Apr 06, 2017
by
Jan Pospisil
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fixed naming style; better test synchronization to the clock
parent
835859a9
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-43
pulseGeneratorTime_tb.vhd
hdl/ffpg/rtl/pulseGeneratorTime_tb.vhd
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hdl/ffpg/rtl/pulseGeneratorTime_tb.vhd
View file @
6f3130c2
...
...
@@ -11,76 +11,76 @@ end entity;
architecture
testbench
of
pulseGeneratorTime_tb
is
constant
CLK_FREQ
:
real
:
=
200
.
0
e6
;
-- in Hz
constant
CLK_PERIOD
:
time
:
=
(
1
.
0
sec
)
/
CLK_FREQ
;
constant
c_ClkFrequency
:
positive
:
=
20
0
e6
;
-- in Hz
constant
c_ClockPeriod
:
time
:
=
(
1
.
0
sec
)
/
c_ClkFrequency
;
constant
PULSE_MIN_WIDTH_TIME
:
time
:
=
20
ns
;
constant
c_PulseMinWidthInTime
:
time
:
=
1
ns
;
signal
clk
,
reset
,
signalIn
,
p
ulseOut
:
std_logic
:
=
'0'
;
signal
lastPulseStart
,
l
astPulseWidth
:
time
:
=
0
ns
;
signal
Clk_k
,
Reset_r
,
SignalIn
,
P
ulseOut
:
std_logic
:
=
'0'
;
signal
LastPulseStart
,
L
astPulseWidth
:
time
:
=
0
ns
;
procedure
tick
(
t
icks
:
in
natural
)
is
begin
wait
for
ticks
*
CLK_PERIOD
;
procedure
f_tick
(
T
icks
:
in
natural
)
is
begin
wait
for
Ticks
*
c_ClockPeriod
;
end
procedure
;
begin
cDUT
:
entity
work
.
pulseGeneratorTime
(
syn
)
i_Dut
:
entity
work
.
pulseGeneratorTime
(
syn
)
generic
map
(
CLK_FREQ
=>
CLK_FREQ
,
PULSE_MIN_WIDTH_TIME
=>
PULSE_MIN_WIDTH_TIME
g_ClkFrequency
=>
c_ClkFrequency
,
g_PulseMinWidthInTime
=>
c_PulseMinWidthInTime
)
port
map
(
cl
k
,
reset
,
s
ignalIn
,
p
ulseOut
Clk_ik
=>
Clk_
k
,
Reset_ir
=>
Reset_r
,
Signal_i
=>
S
ignalIn
,
Pulse_o
=>
P
ulseOut
);
pClk
:
process
is
begin
cl
k
<=
'0'
;
wait
for
CLK_PERIOD
/
2
;
cl
k
<=
'1'
;
wait
for
CLK_PERIOD
/
2
;
Clk_
k
<=
'0'
;
wait
for
c_ClockPeriod
/
2
;
Clk_
k
<=
'1'
;
wait
for
c_ClockPeriod
/
2
;
end
process
;
pPulseWidth
:
process
(
pulseOut
)
is
begin
if
rising_edge
(
pulseOut
)
then
lastPulseStart
<=
now
;
pPulseWidth
:
process
(
PulseOut
)
is
begin
if
rising_edge
(
PulseOut
)
then
LastPulseStart
<=
now
;
else
lastPulseWidth
<=
now
-
l
astPulseStart
;
report
"Last pulse width: "
&
time
'image
(
now
-
l
astPulseStart
);
LastPulseWidth
<=
now
-
L
astPulseStart
;
report
"Last pulse width: "
&
time
'image
(
now
-
L
astPulseStart
);
end
if
;
end
process
;
pTest
:
process
is
variable
L
:
line
;
begin
pTest
:
process
is
begin
-- init wait
tick
(
2
);
f_
tick
(
2
);
-- try single output
signalIn
<=
'1'
;
tick
(
1
);
signalIn
<=
'0'
;
wait
on
lastPulseWidth
;
assert
lastPulseWidth
>=
PULSE_MIN_WIDTH_TIME
wait
until
Clk_k
=
'0'
;
SignalIn
<=
'1'
;
f_tick
(
1
);
SignalIn
<=
'0'
;
wait
on
LastPulseWidth
;
assert
LastPulseWidth
>=
c_PulseMinWidthInTime
report
"Pulse is too short! (1)"
severity
failure
;
-- try multiple inputs
signalIn
<=
'1'
;
tick
(
1
);
signalIn
<=
'0'
;
wait
for
PULSE_MIN_WIDTH_TIME
/
2
;
signalIn
<=
'1'
;
tick
(
1
);
signalIn
<=
'0'
;
wait
on
lastPulseWidth
;
assert
lastPulseWidth
>=
PULSE_MIN_WIDTH_TIME
wait
until
Clk_k
=
'0'
;
SignalIn
<=
'1'
;
f_tick
(
1
);
SignalIn
<=
'0'
;
wait
for
c_PulseMinWidthInTime
/
2
;
wait
until
Clk_k
=
'0'
;
SignalIn
<=
'1'
;
f_tick
(
1
);
SignalIn
<=
'0'
;
wait
on
LastPulseWidth
;
assert
LastPulseWidth
>=
c_PulseMinWidthInTime
report
"Pulse is too short! (1)"
severity
failure
;
assert
false
report
"NONE. End of simulation."
severity
failure
;
wait
;
end
process
;
end
architecture
;
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