Commit 62381b86 authored by Jan Pospisil's avatar Jan Pospisil

comments, typos

parent a814058b
......@@ -4,3 +4,5 @@ AD9512 Fine Delay
The last output (OUT4) from the AD9512 clock divider chip can be delayed. When this fine delay is enabled (i.e. not in bypass mode), delay on this output can be set in 32 steps (0-31). This delay has an offset, so there is still some delay even for step=0 (when not in bypass mode).
This delay is describe here for the 400.789 MHz input clock and the divider set to 2, i.e. 200.3945 MHz clocks on AD9512 outputs. Register field "Ramp Capacitor" needs to be set to 1 and "Ramp Current" to 3 for this case, thus the delay offset is 0.44 ns and full delay range is 1.99 ns adjustable in 32 steps. This yields a delay from 0.44 to 2.43 ns with step of 64 ps. This spans roughly half of the AD9512 output clock period.
Python example: pg.SetClockFineDelay(<step>, 3, 1)
......@@ -42,7 +42,7 @@ entity Ad9512Syncer is
port (
Clk_ik: in std_logic;
StartSync_i: in std_logic; -- one pulse starts synchronization
Trigger_i: in std_logic; -- falling edge of this signals determines synchronization point
Trigger_i: in std_logic; -- rising edge of this signals determines synchronization point
Ad9512Sync_o: out std_logic := '0' -- synchronization pulse for AD9512
end entity;
......@@ -251,6 +251,7 @@ begin
-- LED outputs
-- "TRIG IN" LED can only be blinking if ClkRf_k is present
cTriggerSyncer: entity work.Delay(syn)
generic map (
g_Width => 1,
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