typo

a814058b · Jan Pospisil · df896ba9 · a814058b
Commit a814058b authored Apr 06, 2017 by Jan Pospisil
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Showing with 2 additions and 2 deletions

Testbench.sv hdl/svec/sim/testbench/Testbench.sv +2 -2

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--- a/hdl/svec/sim/testbench/Testbench.sv
+++ b/hdl/svec/sim/testbench/Testbench.sv
@@ -215,7 +215,7 @@ module Testbench;
        WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
    endtask
    
-    task automatic WaitUntilRead;
+    task automatic WaitUntilReady;
        uint32_t data;
        
        do
@@ -230,7 +230,7 @@ module Testbench;
        #20us;
        init_vme64x_core;
        
-        WaitUntilRead;
+        WaitUntilReady;
        
        #5us