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FMC DEL 1ns 2cha
Commit 3db419eb authored by Jan Pospisil's avatar Jan Pospisil
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fixed pulseGenerator for cases when g_PulseMinWidth==1

parent d4ca5732
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Showing with 35 additions and 29 deletions
hdl/ffpg/rtl/pulseGenerator.vhd
View file @ 3db419eb
......@@ -7,41 +7,47 @@ library ieee;
use ieee.std_logic_1164.all;
entity PulseGenerator is
generic (
g_PulseMinWidth: integer := 3 -- multiply of 'Clk_ik' periods
);
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Signal_i: in std_logic;
Pulse_o: out std_logic
);
generic (
g_PulseMinWidth: positive := 3 -- multiple of 'Clk_ik' periods
);
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Signal_i: in std_logic;
Pulse_o: out std_logic
);
end entity;
architecture base of PulseGenerator is
signal ShiftRegister_b: std_logic_vector(g_PulseMinWidth-1 downto 0) := (others => '0');
signal ShiftRegister_b: std_logic_vector(g_PulseMinWidth-1 downto 0) := (others => '0');
begin
pShiftRegister: process (Clk_ik) begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
ShiftRegister_b <= (others => '0');
else
ShiftRegister_b <= ShiftRegister_b(g_PulseMinWidth-2 downto 0)&Signal_i;
end if;
end if;
end process;
pPulseGenerator: process (ShiftRegister_b) is
variable Pulse: std_logic := '0';
begin
Pulse := '0';
for i in ShiftRegister_b'range loop
Pulse := Pulse or ShiftRegister_b(i);
end loop;
Pulse_o <= Pulse;
end process;
gMore: if g_PulseMinWidth > 1 generate
pShiftRegister: process (Clk_ik) begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
ShiftRegister_b <= (others => '0');
else
ShiftRegister_b <= ShiftRegister_b(g_PulseMinWidth-2 downto 0)&Signal_i;
end if;
end if;
end process;
pPulseGenerator: process (ShiftRegister_b) is
variable Pulse: std_logic := '0';
begin
Pulse := '0';
for i in ShiftRegister_b'range loop
Pulse := Pulse or ShiftRegister_b(i);
end loop;
Pulse_o <= Pulse;
end process;
end generate;
gOne: if g_PulseMinWidth = 1 generate
Pulse_o <= Signal_i;
end generate;
end architecture;
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