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F
FMC DEL 1ns 2cha
Commit 8781787e authored by Jan Pospisil's avatar Jan Pospisil
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added option for better UVM debug

parent 1ca03bbf
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hdl/ffpg/sim/testbench/sim
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# start simulation, set waveform, run simulation
vsim -voptargs=+acc work.Testbench
vsim -classdebug -voptargs=+acc work.Testbench
add wave -group Interface -r sim:/Testbench/LocalInterface/*
add wave -group DUT sim:/Testbench/dut/cFfpgCore/cFfpgSlave/*
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