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FMC DEL 1ns 2cha
Commit df896ba9 authored by Jan Pospisil's avatar Jan Pospisil
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fixed DelayController logic and port naming (LEN port for delay chips)

parent 6f3130c2
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Showing with 130 additions and 114 deletions
hdl/ffpg/rtl/DelayController.vhd
View file @ df896ba9
......@@ -51,10 +51,10 @@ entity DelayController is
Ch2ResValue_ib: in unsigned(9 downto 0);
Ch2ResValueLoad_i: in std_logic;
DelayValue_ob: out unsigned(9 downto 0);
Ch1SetLe_o: out std_logic;
Ch1ResLe_o: out std_logic;
Ch2SetLe_o: out std_logic;
Ch2ResLe_o: out std_logic;
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
Ch2ResLe_on: out std_logic;
Busy_o: out std_logic
);
end entity;
......@@ -75,27 +75,29 @@ begin
ActiveOutput <= e_None;
DelayValue_ob <= (others => '0');
StartConfiguration <= '0';
elsif LoadPulse = '0' then
else
StartConfiguration <= '0';
if Ch1SetValueLoad_i = '1' then
ActiveOutput <= e_Ch1Set;
DelayValue_ob <= Ch1SetValue_ib;
StartConfiguration <= '1';
end if;
if Ch1ResValueLoad_i = '1' then
ActiveOutput <= e_Ch1Res;
DelayValue_ob <= Ch1ResValue_ib;
StartConfiguration <= '1';
end if;
if Ch2SetValueLoad_i = '1' then
ActiveOutput <= e_Ch2Set;
DelayValue_ob <= Ch2SetValue_ib;
StartConfiguration <= '1';
end if;
if Ch2ResValueLoad_i = '1' then
ActiveOutput <= e_Ch2Res;
DelayValue_ob <= Ch2ResValue_ib;
StartConfiguration <= '1';
if LoadPulse = '0' then
if Ch1SetValueLoad_i = '1' then
ActiveOutput <= e_Ch1Set;
DelayValue_ob <= Ch1SetValue_ib;
StartConfiguration <= '1';
end if;
if Ch1ResValueLoad_i = '1' then
ActiveOutput <= e_Ch1Res;
DelayValue_ob <= Ch1ResValue_ib;
StartConfiguration <= '1';
end if;
if Ch2SetValueLoad_i = '1' then
ActiveOutput <= e_Ch2Set;
DelayValue_ob <= Ch2SetValue_ib;
StartConfiguration <= '1';
end if;
if Ch2ResValueLoad_i = '1' then
ActiveOutput <= e_Ch2Res;
DelayValue_ob <= Ch2ResValue_ib;
StartConfiguration <= '1';
end if;
end if;
end if;
end if;
......@@ -113,16 +115,16 @@ begin
Pulse_o => LoadPulse
);
Ch1SetLe_o <=
Ch1SetLe_on <=
'0' when (ActiveOutput = e_Ch1Set) and LoadPulse = '1' else
'1';
Ch1ResLe_o <=
Ch1ResLe_on <=
'0' when (ActiveOutput = e_Ch1Res) and LoadPulse = '1' else
'1';
Ch2SetLe_o <=
Ch2SetLe_on <=
'0' when (ActiveOutput = e_Ch2Set) and LoadPulse = '1' else
'1';
Ch2ResLe_o <=
Ch2ResLe_on <=
'0' when (ActiveOutput = e_Ch2Res) and LoadPulse = '1' else
'1';
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ df896ba9
......@@ -62,10 +62,10 @@ entity FfpgCore is
Ch2OutputEnable_o: out std_logic;
-- delay configuration
DelayValue_ob: out unsigned(9 downto 0);
Ch1SetLe_o: out std_logic;
Ch1ResLe_o: out std_logic;
Ch2SetLe_o: out std_logic;
Ch2ResLe_o: out std_logic;
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
Ch2ResLe_on: out std_logic;
--
Ch1Set_o: out std_logic;
Ch1Res_o: out std_logic;
......@@ -212,10 +212,10 @@ begin
Ch1OutputEnable_o => Ch1OutputEnable_o,
Ch2OutputEnable_o => Ch2OutputEnable_o,
DelayValue_ob => DelayValue_ob,
Ch1SetLe_o => Ch1SetLe_o,
Ch1ResLe_o => Ch1ResLe_o,
Ch2SetLe_o => Ch2SetLe_o,
Ch2ResLe_o => Ch2ResLe_o,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
Ch2SetLe_on => Ch2SetLe_on,
Ch2ResLe_on => Ch2ResLe_on,
Ch1Set_o => Ch1Set_o,
Ch1Res_o => Ch1Res_o,
Ch2Set_o => Ch2Set_o,
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ df896ba9
......@@ -69,10 +69,10 @@ entity FfpgSlave is
Ch2OutputEnable_o: out std_logic;
-- delay configuration
DelayValue_ob: out unsigned(9 downto 0);
Ch1SetLe_o: out std_logic;
Ch1ResLe_o: out std_logic;
Ch2SetLe_o: out std_logic;
Ch2ResLe_o: out std_logic;
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
Ch2ResLe_on: out std_logic;
--
Ch1Set_o: out std_logic;
Ch1Res_o: out std_logic;
......@@ -193,10 +193,10 @@ begin
Ch2ResValue_ib => WbRegsOutput.ch2_delay_reset_o,
Ch2ResValueLoad_i => WbRegsOutput.ch2_delay_reset_load_o,
DelayValue_ob => DelayValue_ob,
Ch1SetLe_o => Ch1SetLe_o,
Ch1ResLe_o => Ch1ResLe_o,
Ch2SetLe_o => Ch2SetLe_o,
Ch2ResLe_o => Ch2ResLe_o,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
Ch2SetLe_on => Ch2SetLe_on,
Ch2ResLe_on => Ch2ResLe_on,
Busy_o => WbRegsInput.status_delay_configuration_busy_i
);
......
hdl/ffpg/sim/testbench/FfpgCoreWrapper.vhd
View file @ df896ba9
......@@ -68,10 +68,10 @@ entity FfpgCoreWrapper is
Ch1OutputEnable_o: out std_logic;
Ch2OutputEnable_o: out std_logic;
DelayValue_ob: out unsigned(9 downto 0);
Ch1SetLe_o: out std_logic;
Ch1ResLe_o: out std_logic;
Ch2SetLe_o: out std_logic;
Ch2ResLe_o: out std_logic;
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
Ch2ResLe_on: out std_logic;
Ch1Set_o: out std_logic;
Ch1Res_o: out std_logic;
Ch2Set_o: out std_logic;
......@@ -118,10 +118,10 @@ begin
Ch1OutputEnable_o => Ch1OutputEnable_o,
Ch2OutputEnable_o => Ch2OutputEnable_o,
DelayValue_ob => DelayValue_ob,
Ch1SetLe_o => Ch1SetLe_o,
Ch1ResLe_o => Ch1ResLe_o,
Ch2SetLe_o => Ch2SetLe_o,
Ch2ResLe_o => Ch2ResLe_o,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
Ch2SetLe_on => Ch2SetLe_on,
Ch2ResLe_on => Ch2ResLe_on,
Ch1Set_o => Ch1Set_o,
Ch1Res_o => Ch1Res_o,
Ch2Set_o => Ch2Set_o,
......
hdl/ffpg/sim/testbench/Testbench.sv
View file @ df896ba9
......@@ -74,10 +74,10 @@ module Testbench;
.Ch1OutputEnable_o(), // not tested so far
.Ch2OutputEnable_o(), // not tested so far
.DelayValue_ob(), // not tested so far
.Ch1SetLe_o(), // not tested so far
.Ch1ResLe_o(), // not tested so far
.Ch2SetLe_o(), // not tested so far
.Ch2ResLe_o(), // not tested so far
.Ch1SetLe_on(), // not tested so far
.Ch1ResLe_on(), // not tested so far
.Ch2SetLe_on(), // not tested so far
.Ch2ResLe_on(), // not tested so far
.Ch1Set_o(LocalInterface.Fmc.Ch1Set),
.Ch1Res_o(LocalInterface.Fmc.Ch1Res),
.Ch2Set_o(LocalInterface.Fmc.Ch2Set),
......@@ -116,11 +116,11 @@ module Testbench;
uvm_top.finish_on_completion = 0; // not to finish when GUI is used
// run_test("TestTriggerAdc");
// run_test("TestDelayConfiguration");
run_test("TestDelayConfiguration");
// run_test("TestPulseGenerationBlind");
// run_test("TestPulseGenerationSequential");
// run_test("TestPulseGeneration");
run_test("TestAd9512Communication");
// run_test("TestAd9512Communication");
$stop();
end
......
hdl/svec/rtl/SvecTopFfpg.vhd
View file @ df896ba9
......@@ -137,10 +137,10 @@ entity SvecTopFfpg is
Fmc0Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc0DelayValue_ob: out unsigned(9 downto 0);
Fmc0Ch1SetLe_o: out std_logic;
Fmc0Ch1ResLe_o: out std_logic;
Fmc0Ch2SetLe_o: out std_logic;
Fmc0Ch2ResLe_o: out std_logic;
Fmc0Ch1SetLe_on: out std_logic;
Fmc0Ch1ResLe_on: out std_logic;
Fmc0Ch2SetLe_on: out std_logic;
Fmc0Ch2ResLe_on: out std_logic;
Fmc0Ch1SetP_o: out std_logic;
Fmc0Ch1SetN_o: out std_logic;
Fmc0Ch1ResP_o: out std_logic;
......@@ -186,10 +186,10 @@ entity SvecTopFfpg is
Fmc1Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc1DelayValue_ob: out unsigned(9 downto 0);
Fmc1Ch1SetLe_o: out std_logic;
Fmc1Ch1ResLe_o: out std_logic;
Fmc1Ch2SetLe_o: out std_logic;
Fmc1Ch2ResLe_o: out std_logic;
Fmc1Ch1SetLe_on: out std_logic;
Fmc1Ch1ResLe_on: out std_logic;
Fmc1Ch2SetLe_on: out std_logic;
Fmc1Ch2ResLe_on: out std_logic;
Fmc1Ch1SetP_o: out std_logic;
Fmc1Ch1SetN_o: out std_logic;
Fmc1Ch1ResP_o: out std_logic;
......@@ -760,10 +760,10 @@ begin
Ch2OutputEnable_o => Fmc0Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => Fmc0DelayValue_ob,
Ch1SetLe_o => Fmc0Ch1SetLe_o,
Ch1ResLe_o => Fmc0Ch1ResLe_o,
Ch2SetLe_o => Fmc0Ch2SetLe_o,
Ch2ResLe_o => Fmc0Ch2ResLe_o,
Ch1SetLe_on => Fmc0Ch1SetLe_on,
Ch1ResLe_on => Fmc0Ch1ResLe_on,
Ch2SetLe_on => Fmc0Ch2SetLe_on,
Ch2ResLe_on => Fmc0Ch2ResLe_on,
Ch1Set_o => Fmc0Ch1Set,
Ch1Res_o => Fmc0Ch1Res,
Ch2Set_o => Fmc0Ch2Set,
......@@ -888,10 +888,10 @@ begin
Ch2OutputEnable_o => Fmc1Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => Fmc1DelayValue_ob,
Ch1SetLe_o => Fmc1Ch1SetLe_o,
Ch1ResLe_o => Fmc1Ch1ResLe_o,
Ch2SetLe_o => Fmc1Ch2SetLe_o,
Ch2ResLe_o => Fmc1Ch2ResLe_o,
Ch1SetLe_on => Fmc1Ch1SetLe_on,
Ch1ResLe_on => Fmc1Ch1ResLe_on,
Ch2SetLe_on => Fmc1Ch2SetLe_on,
Ch2ResLe_on => Fmc1Ch2ResLe_on,
Ch1Set_o => Fmc1Ch1Set,
Ch1Res_o => Fmc1Ch1Res,
Ch2Set_o => Fmc1Ch2Set,
......
hdl/svec/sim/testbench/SvecTopFfpgWrapper.vhd
View file @ df896ba9
......@@ -122,12 +122,15 @@ entity SvecTopFfpgWrapper is
-- output enable
Fmc0Ch1OutputEnable_o: out std_logic;
Fmc0Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc0Ch1OutCal_i: in std_logic;
Fmc0Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc0DelayValue_ob: out std_logic_vector(9 downto 0);
Fmc0Ch1SetLe_o: out std_logic;
Fmc0Ch1ResLe_o: out std_logic;
Fmc0Ch2SetLe_o: out std_logic;
Fmc0Ch2ResLe_o: out std_logic;
Fmc0Ch1SetLe_on: out std_logic;
Fmc0Ch1ResLe_on: out std_logic;
Fmc0Ch2SetLe_on: out std_logic;
Fmc0Ch2ResLe_on: out std_logic;
Fmc0Ch1SetP_o: out std_logic;
Fmc0Ch1SetN_o: out std_logic;
Fmc0Ch1ResP_o: out std_logic;
......@@ -172,12 +175,15 @@ entity SvecTopFfpgWrapper is
-- output enable
Fmc1Ch1OutputEnable_o: out std_logic;
Fmc1Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc1Ch1OutCal_i: in std_logic;
Fmc1Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc1DelayValue_ob: out std_logic_vector(9 downto 0);
Fmc1Ch1SetLe_o: out std_logic;
Fmc1Ch1ResLe_o: out std_logic;
Fmc1Ch2SetLe_o: out std_logic;
Fmc1Ch2ResLe_o: out std_logic;
Fmc1Ch1SetLe_on: out std_logic;
Fmc1Ch1ResLe_on: out std_logic;
Fmc1Ch2SetLe_on: out std_logic;
Fmc1Ch2ResLe_on: out std_logic;
Fmc1Ch1SetP_o: out std_logic;
Fmc1Ch1SetN_o: out std_logic;
Fmc1Ch1ResP_o: out std_logic;
......@@ -279,11 +285,13 @@ begin
Fmc0VcxoDac_o.SerialData => Fmc0VcxoDac_o_SerialData,
Fmc0Ch1OutputEnable_o => Fmc0Ch1OutputEnable_o,
Fmc0Ch2OutputEnable_o => Fmc0Ch2OutputEnable_o,
Fmc0Ch1OutCal_i => Fmc0Ch1OutCal_i,
Fmc0Ch2OutCal_i => Fmc0Ch2OutCal_i,
Fmc0DelayValue_ob => Fmc0DelayValue_ob_unsigned,
Fmc0Ch1SetLe_o => Fmc0Ch1SetLe_o,
Fmc0Ch1ResLe_o => Fmc0Ch1ResLe_o,
Fmc0Ch2SetLe_o => Fmc0Ch2SetLe_o,
Fmc0Ch2ResLe_o => Fmc0Ch2ResLe_o,
Fmc0Ch1SetLe_on => Fmc0Ch1SetLe_on,
Fmc0Ch1ResLe_on => Fmc0Ch1ResLe_on,
Fmc0Ch2SetLe_on => Fmc0Ch2SetLe_on,
Fmc0Ch2ResLe_on => Fmc0Ch2ResLe_on,
Fmc0Ch1SetP_o => Fmc0Ch1SetP_o,
Fmc0Ch1SetN_o => Fmc0Ch1SetN_o,
Fmc0Ch1ResP_o => Fmc0Ch1ResP_o,
......@@ -317,11 +325,13 @@ begin
Fmc1VcxoDac_o.SerialData => Fmc1VcxoDac_o_SerialData,
Fmc1Ch1OutputEnable_o => Fmc1Ch1OutputEnable_o,
Fmc1Ch2OutputEnable_o => Fmc1Ch2OutputEnable_o,
Fmc1Ch1OutCal_i => Fmc1Ch1OutCal_i,
Fmc1Ch2OutCal_i => Fmc1Ch2OutCal_i,
Fmc1DelayValue_ob => Fmc1DelayValue_ob_unsigned,
Fmc1Ch1SetLe_o => Fmc1Ch1SetLe_o,
Fmc1Ch1ResLe_o => Fmc1Ch1ResLe_o,
Fmc1Ch2SetLe_o => Fmc1Ch2SetLe_o,
Fmc1Ch2ResLe_o => Fmc1Ch2ResLe_o,
Fmc1Ch1SetLe_on => Fmc1Ch1SetLe_on,
Fmc1Ch1ResLe_on => Fmc1Ch1ResLe_on,
Fmc1Ch2SetLe_on => Fmc1Ch2SetLe_on,
Fmc1Ch2ResLe_on => Fmc1Ch2ResLe_on,
Fmc1Ch1SetP_o => Fmc1Ch1SetP_o,
Fmc1Ch1SetN_o => Fmc1Ch1SetN_o,
Fmc1Ch1ResP_o => Fmc1Ch1ResP_o,
......
hdl/svec/sim/testbench/fmc.svh
View file @ df896ba9
......@@ -10,11 +10,13 @@
logic Fmc``__nb``VcxoDac_o_SerialData; \
logic Fmc``__nb``Ch1OutputEnable_o; \
logic Fmc``__nb``Ch2OutputEnable_o; \
logic Fmc``__nb``Ch1OutCal_i; \
logic Fmc``__nb``Ch2OutCal_i; \
logic [9:0] Fmc``__nb``DelayValue_ob; \
logic Fmc``__nb``Ch1SetLe_o; \
logic Fmc``__nb``Ch1ResLe_o; \
logic Fmc``__nb``Ch2SetLe_o; \
logic Fmc``__nb``Ch2ResLe_o; \
logic Fmc``__nb``Ch1SetLe_on; \
logic Fmc``__nb``Ch1ResLe_on; \
logic Fmc``__nb``Ch2SetLe_on; \
logic Fmc``__nb``Ch2ResLe_on; \
logic Fmc``__nb``Ch1SetP_o; \
logic Fmc``__nb``Ch1SetN_o; \
logic Fmc``__nb``Ch1ResP_o; \
......@@ -50,11 +52,13 @@
.Fmc``__nb``VcxoDac_o_SerialData(Fmc``__nb``VcxoDac_o_SerialData), \
.Fmc``__nb``Ch1OutputEnable_o(Fmc``__nb``Ch1OutputEnable_o), \
.Fmc``__nb``Ch2OutputEnable_o(Fmc``__nb``Ch2OutputEnable_o), \
.Fmc``__nb``Ch1OutCal_i(Fmc``__nb``Ch1OutCal_i), \
.Fmc``__nb``Ch2OutCal_i(Fmc``__nb``Ch2OutCal_i), \
.Fmc``__nb``DelayValue_ob(Fmc``__nb``DelayValue_ob), \
.Fmc``__nb``Ch1SetLe_o(Fmc``__nb``Ch1SetLe_o), \
.Fmc``__nb``Ch1ResLe_o(Fmc``__nb``Ch1ResLe_o), \
.Fmc``__nb``Ch2SetLe_o(Fmc``__nb``Ch2SetLe_o), \
.Fmc``__nb``Ch2ResLe_o(Fmc``__nb``Ch2ResLe_o), \
.Fmc``__nb``Ch1SetLe_on(Fmc``__nb``Ch1SetLe_on), \
.Fmc``__nb``Ch1ResLe_on(Fmc``__nb``Ch1ResLe_on), \
.Fmc``__nb``Ch2SetLe_on(Fmc``__nb``Ch2SetLe_on), \
.Fmc``__nb``Ch2ResLe_on(Fmc``__nb``Ch2ResLe_on), \
.Fmc``__nb``Ch1SetP_o(Fmc``__nb``Ch1SetP_o), \
.Fmc``__nb``Ch1SetN_o(Fmc``__nb``Ch1SetN_o), \
.Fmc``__nb``Ch1ResP_o(Fmc``__nb``Ch1ResP_o), \
......
hdl/svec/syn/SvecFfpg.ucf
View file @ df896ba9
......@@ -351,8 +351,8 @@ NET "Fmc1Present_in" IOSTANDARD = "LVCMOS33";
NET "Fmc0ClkIn0P_ik" LOC = C16; # fmc0_la_p[0]
NET "Fmc0ClkIn0P_ik" IOSTANDARD = "LVDS_25";
NET "Fmc0Ch1ResLe_o" LOC = H21; # fmc0_la_p[1]
NET "Fmc0Ch1ResLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1ResLe_on" LOC = H21; # fmc0_la_p[1]
NET "Fmc0Ch1ResLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1SetP_o" LOC = J22; # fmc0_la_p[2]
NET "Fmc0Ch1SetP_o" IOSTANDARD = "LVDS_25";
NET "Fmc0Onewire_io" LOC = E25; # fmc0_la_p[3]
......@@ -401,8 +401,8 @@ NET "Fmc0DelayValue_ob[7]" LOC = G10; # fmc0_la_p[24]
NET "Fmc0DelayValue_ob[7]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[6]" LOC = F11; # fmc0_la_p[25]
NET "Fmc0DelayValue_ob[6]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2ResLe_o" LOC = L14; # fmc0_la_p[26]
NET "Fmc0Ch2ResLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2ResLe_on" LOC = L14; # fmc0_la_p[26]
NET "Fmc0Ch2ResLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0VcxoDac_o_SerialClock" LOC = M13; # fmc0_la_p[27]
NET "Fmc0VcxoDac_o_SerialClock" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[28]" LOC = L12;
......@@ -420,8 +420,8 @@ NET "Fmc0SpiAd9512Miso_i" IOSTANDARD = "LVCMOS25";
NET "Fmc0ClkIn0N_ik" LOC = A16; # fmc0_la_n[0]
NET "Fmc0ClkIn0N_ik" IOSTANDARD = "LVDS_25";
NET "Fmc0Ch1SetLe_o" LOC = G21; # fmc0_la_n[1]
NET "Fmc0Ch1SetLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1SetLe_on" LOC = G21; # fmc0_la_n[1]
NET "Fmc0Ch1SetLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1SetN_o" LOC = H22; # fmc0_la_n[2]
NET "Fmc0Ch1SetN_o" IOSTANDARD = "LVDS_25";
# NET "fmc0_la_n[3]" LOC = D25;
......@@ -470,8 +470,8 @@ NET "Fmc0DelayValue_ob[9]" LOC = F10; # fmc0_la_n[24]
NET "Fmc0DelayValue_ob[9]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[8]" LOC = E11; # fmc0_la_n[25]
NET "Fmc0DelayValue_ob[8]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2SetLe_o" LOC = K14; # fmc0_la_n[26]
NET "Fmc0Ch2SetLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2SetLe_on" LOC = K14; # fmc0_la_n[26]
NET "Fmc0Ch2SetLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0VcxoDac_o_SerialData" LOC = L13; # fmc0_la_n[27]
NET "Fmc0VcxoDac_o_SerialData" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[28]" LOC = K12;
......@@ -525,8 +525,8 @@ NET "Fmc0SpiAd9512Cs_on" IOSTANDARD = "LVCMOS25";
NET "Fmc1ClkIn0P_ik" LOC = AJ17; # fmc1_la_p[0]
NET "Fmc1ClkIn0P_ik" IOSTANDARD = "LVDS_25";
NET "Fmc1Ch1ResLe_o" LOC = AG8; # fmc1_la_p[1]
NET "Fmc1Ch1ResLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch1ResLe_on" LOC = AG8; # fmc1_la_p[1]
NET "Fmc1Ch1ResLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch1SetP_o" LOC = AC11; # fmc1_la_p[2]
NET "Fmc1Ch1SetP_o" IOSTANDARD = "LVDS_25";
NET "Fmc1Onewire_io" LOC = AE13; # fmc1_la_p[3]
......@@ -575,8 +575,8 @@ NET "Fmc1DelayValue_ob[7]" LOC = AB21; # fmc1_la_p[24]
NET "Fmc1DelayValue_ob[7]" IOSTANDARD = "LVCMOS25";
NET "Fmc1DelayValue_ob[6]" LOC = AB17; # fmc1_la_p[25]
NET "Fmc1DelayValue_ob[6]" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch2ResLe_o" LOC = AC19; # fmc1_la_p[26]
NET "Fmc1Ch2ResLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch2ResLe_on" LOC = AC19; # fmc1_la_p[26]
NET "Fmc1Ch2ResLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc1VcxoDac_o_SerialClock" LOC = AB20; # fmc1_la_p[27]
NET "Fmc1VcxoDac_o_SerialClock" IOSTANDARD = "LVCMOS25";
# NET "fmc1_la_p[28]" LOC = AA22;
......@@ -594,8 +594,8 @@ NET "Fmc1SpiAd9512Miso_i" IOSTANDARD = "LVCMOS25";
NET "Fmc1ClkIn0N_ik" LOC = AK17; # fmc1_la_n[0]
NET "Fmc1ClkIn0N_ik" IOSTANDARD = "LVDS_25";
NET "Fmc1Ch1SetLe_o" LOC = AH8; # fmc1_la_n[1]
NET "Fmc1Ch1SetLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch1SetLe_on" LOC = AH8; # fmc1_la_n[1]
NET "Fmc1Ch1SetLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch1SetN_o" LOC = AD11; # fmc1_la_n[2]
NET "Fmc1Ch1SetN_o" IOSTANDARD = "LVDS_25";
# NET "fmc1_la_n[3]" LOC = AF13;
......@@ -644,8 +644,8 @@ NET "Fmc1DelayValue_ob[9]" LOC = AC21; # fmc1_la_n[24]
NET "Fmc1DelayValue_ob[9]" IOSTANDARD = "LVCMOS25";
NET "Fmc1DelayValue_ob[8]" LOC = AD17; # fmc1_la_n[25]
NET "Fmc1DelayValue_ob[8]" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch2SetLe_o" LOC = AD19; # fmc1_la_n[26]
NET "Fmc1Ch2SetLe_o" IOSTANDARD = "LVCMOS25";
NET "Fmc1Ch2SetLe_on" LOC = AD19; # fmc1_la_n[26]
NET "Fmc1Ch2SetLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc1VcxoDac_o_SerialData" LOC = AC20; # fmc1_la_n[27]
NET "Fmc1VcxoDac_o_SerialData" IOSTANDARD = "LVCMOS25";
# NET "fmc1_la_n[28]" LOC = AC22;
......
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