Rename Fsm.vhd -> DelayedPulseGeneratorFsm.vhd

f33b2d1c · Tom Levens · f7b7c9a0 · f33b2d1c · f33b2d1c · f33b2d1c
Commit f33b2d1c authored Feb 23, 2023 by Tom Levens
3 changed files
--- a/hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
@@ -120,7 +120,7 @@ begin
        end if;
    end process;

-    cFsm: entity work.Fsm(syn)
+    cFsm: entity work.DelayedPulseGeneratorFsm(syn)
        port map (
            Clk_ik => Clk_ik,
            Reset_ir => Reset_ir,

--- a/hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
@@ -3,7 +3,7 @@
 -- Project    : FMC DEL 1ns 2cha (FFPG)
 -- URL        : http://www.ohwr.org/projects/fmc-del-1ns-2cha
 -------------------------------------------------------------------------------
-- File       : Fsm.vhd
+-- File       : DelayedPulseGeneratorFsm.vhd
 -- Author(s)  : Jan Pospisil <j.pospisil@cern.ch>
 -- Company    : CERN (BE-BI-QP)
 -- Created    : 2016-07-05
@@ -38,7 +38,7 @@ use ieee.numeric_std.all;

 use work.FfpgPkg.all;

-entity Fsm is
+entity DelayedPulseGeneratorFsm is
    port (
        -- main signals
        Clk_ik: in std_logic;
@@ -57,7 +57,7 @@ entity Fsm is
    );
 end entity;

-architecture syn of Fsm is
+architecture syn of DelayedPulseGeneratorFsm is

    type t_State is (
        s_Stop,

--- a/hdl/svec/syn/SvecFfpg.xise
+++ b/hdl/svec/syn/SvecFfpg.xise
@@ -406,7 +406,7 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    </file>
-    <file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorFsm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    </file>