Commit decd2b22 authored by Jan Pospisil's avatar Jan Pospisil

added few words about how to test the board

parent c2bf9a5f
......@@ -21,4 +21,29 @@ Implementation
end function;
(This step is not needed when ./hdl/ip_cores/wishbone-gen_patches are applied.)
X) synthesize .\hdl\svec\syn\SvecFfpg.xise
\ No newline at end of file
X) synthesize .\hdl\svec\syn\SvecFfpg.xise
The "!->" determines what to check further when check fails.
1) Plug FMC mezzanine into SVEC carrier board and into VME crate (and configure properly)
2) When using FMC mezzanine version 2 (EDA-03339-V2), check that all power LEDs (LD1, LD2, LD3) are on (!-> SVEC fuses, power supplies)
3) Connect clock (CLK IN) f_CLK = 400.789 MHz and trigger (TRIG IN) f_TRIG = 11.245 kHz - trigger has to be phase aligned with clock
4) Use /sw/ to configure the GW and run some test
5) Check:
a) There is f_CLK/2 clock present on CLK OUT (!-> AD9512 divider)
b) LED CLK IN is on (!-> clock source is not stable?)
c) python: PrintFrequency(pg) should return also f_CLK/2 (!-> clock infrastructure)
d) LED TRIG IN is blinking (!-> trigger input)
e) python: pg.PrintDebug() should display "CHx FSM state: Outputting" (!-> "WaitForTrigger" - check trigger input; "Stop" - check channel configuration)
f) python: pg.PrintStatus() should display "Channel x output: enabled" and "Channel 1: running" (!-> channel configuration)
g) LED OUT x is on (!-> channel configuration)
h) there is/are pulse(s) on the OUT x output
To isolate output stage (optical switch and fuse) error, you can use front panel LEMO connectors. When channel output is disabled (schematic: OUT_EN_x, python: CHx_OE), output is redirected from front panel connector to FMC feedback loop back to FPGA (schematic CAL_OUT_2). These signal are connected to the SVEC front panel LEMO connectors with this mapping:
LEMO 1 - FMC2, channel 1
LEMO 2 - FMC2, channel 2
LEMO 3 - FMC1, channel 1
LEMO 4 - FMC1, channel 2
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