Avoid gc_sync_register ISE error

The SVEC base design has constraints for gc_sync_register but this is never instantiated in this design. Therefore ISE gives an error during synthesis. To avoid this error I have added an extra "dummy" gc_sync_register for synchronising the FP GPIO inputs. This can be removed once this issue is resolved: https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25

Avoid gc_sync_register ISE error
The SVEC base design has constraints for gc_sync_register but this is never instantiated in this design. Therefore ISE gives an error during synthesis. To avoid this error I have added an extra "dummy" gc_sync_register for synchronising the FP GPIO inputs. This can be removed once this issue is resolved: https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25
fc03fc63 · Tom Levens · 4e5cb99a · fc03fc63
Commit fc03fc63 authored Feb 25, 2023 by Tom Levens
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svec_top_ffpg.vhd hdl/top/svec/svec_top_ffpg.vhd +19 -3

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--- a/hdl/top/svec/svec_top_ffpg.vhd
+++ b/hdl/top/svec/svec_top_ffpg.vhd
@@ -326,6 +326,7 @@ architecture top of svec_top_ffpg is
  signal vme_access     : std_logic;

  signal fp_gpio_in     : std_logic_vector(4 downto 1);
+  signal fp_gpio_sync   : std_logic_vector(4 downto 1);
  signal fp_gpio        : std_logic_vector(4 downto 1);
  signal fp_gpio_led    : std_logic_vector(4 downto 1);

@@ -590,20 +591,35 @@ begin
  fp_gpio_in(3) <= fp_gpio3_b;
  fp_gpio_in(4) <= fp_gpio4_b;

+  -- TODO: I put an extra gc_sync_register here to keep ISE happy as the
+  -- SVEC base design has constraints for it. This can be removed once
+  -- this issue is resolved:
+  --   https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25
+  cmp_fp_gpio_sync_register: gc_sync_register
+    generic map (
+      g_width   => 4
+    )
+    port map (
+      clk_i     => clk_sys_62m5,
+      rst_n_a_i => rst_sys_62m5_n,
+      d_i       => fp_gpio_in,
+      q_o       => fp_gpio_sync
+    );
+
  -- Front panel IO synchronisation
  gen_fp_gpio_sync: for i in 1 to 4 generate
    begin
-      cmp_fp_gpio_sync: gc_sync_ffs
+      cmp_fp_gpio_sync_ffs: gc_sync_ffs
        port map (
          clk_i    => clk_sys_62m5,
          rst_n_i  => '1',
-          data_i   => fp_gpio_in(i),
+          data_i   => fp_gpio_sync(i),
          ppulse_o => fp_gpio(i)
        );

      cmp_fp_gpio_led : gc_extend_pulse
        generic map (
-          g_width => 2500000
+          g_width    => 2500000
        )
        port map (
          clk_i      => clk_sys_62m5,