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FMC DEL 1ns 2cha
Commit c06f91c8 authored by Tom Levens's avatar Tom Levens
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HISTORY.txt
View file @ c06f91c8
v1.4, 2017-04-10
added more documentation
added Python CLI
fixed inverted pulse mode
updated submodules general-cores, vme64x-core and uvm_agents
added wbgen2 generated files
added WB-SPI core for AD9512 (can override HW control)
added signal back loop (connected to front panel LEMOs)
typos, small bugfixes
v1.3, 2016-09-21
transformed Python driver to OOP code, simplified interface
fixed temperature readout
improved timing of the SET/RES pulses (IOB registers, timing constraints)
added AD9512 OUT4 fine delay control
added trigger latency calibration example code
v1.2, 2016-09-05
introduced independent Trigger Latency for the two channels
updated Python driver
v1.1, 2016-09-01
added patches used on submodules during development of v1.0
added version numbers (major.minor.rev)
added clock_stable status bit
added option for negative pulses
added HISTORY.txt
v1.0, 2016-08-24
first official release
v1.4, 2017-04-10
added more documentation
added Python CLI
fixed inverted pulse mode
updated submodules general-cores, vme64x-core and uvm_agents
added wbgen2 generated files
added WB-SPI core for AD9512 (can override HW control)
added signal back loop (connected to front panel LEMOs)
typos, small bugfixes
v1.3, 2016-09-21
transformed Python driver to OOP code, simplified interface
fixed temperature readout
improved timing of the SET/RES pulses (IOB registers, timing constraints)
added AD9512 OUT4 fine delay control
added trigger latency calibration example code
v1.2, 2016-09-05
introduced independent Trigger Latency for the two channels
updated Python driver
v1.1, 2016-09-01
added patches used on submodules during development of v1.0
added version numbers (major.minor.rev)
added clock_stable status bit
added option for negative pulses
added HISTORY.txt
v1.0, 2016-08-24
first official release
doc/FFPG-module-specification.txt
View file @ c06f91c8
......@@ -7,39 +7,39 @@ A) Controllable blocks and connections on the card
--------------------------------------------------
1) Clock selection and configuration
3 Variants
1) external clock (front panel)
2) loop clk (from FPGA)
3) on-board clock generator
communications
SPI/QSPI/Microwire/DSP <- FMC ("SPI_VCXO", AD5660)
1bit <- FMC ("CLK2_SEL", SY58017U)
SPI/SSR <-> FMC ("SPI_AD9512", AD9512)
3 Variants
1) external clock (front panel)
2) loop clk (from FPGA)
3) on-board clock generator
communications
SPI/QSPI/Microwire/DSP <- FMC ("SPI_VCXO", AD5660)
1bit <- FMC ("CLK2_SEL", SY58017U)
SPI/SSR <-> FMC ("SPI_AD9512", AD9512)
2) channels configuration (2 times, MC100EP195B)
2bits <- FMC (LE_SET, LE_RES)
10bits <- FMC (shared)
1bit <- FMC (OUT_EN)
1bit -> FMC (CAL_OUT)
2bits <- FMC (LE_SET, LE_RES)
10bits <- FMC (shared)
1bit <- FMC (OUT_EN)
1bit -> FMC (CAL_OUT)
3) channels controlling (2 times)
2diff <- FMC (IN_SET, IN_RES)
2diff <- FMC (IN_SET, IN_RES)
4) Trigger threshold (AD5660)
SPI/QSPI/Microwire/DSP <- FMC ("SPI_DAC")
SPI/QSPI/Microwire/DSP <- FMC ("SPI_DAC")
6) Thermometer (DS18B20)
1wire <-> FMC ("onewire")
1wire <-> FMC ("onewire")
7) LEDs
4bits <- FMC
4bits <- FMC
8) Clock synchronization
1bit <- FMC ("AD9152_FUNC", AD9512)
X) Serial EEPROM (24AA64T)
I2C + address <-> FMC
(Handled by FMC carrier board)
I2C + address <-> FMC
(Handled by FMC carrier board)
B) Controlling module logic
---------------------------
......@@ -147,6 +147,6 @@ B) Controlling module logic
signal will be used for this synchronization. Synchronization will be done on request via WB
register. Status of the last synchronization (success/failure) will be signalized by one bit in
the WB status register.
X) Others: FMC outputs CAL_OUT coming from channels will not be used. The loop clock from FPGA
coming to FMC card will carry WB clock used by the FPGA module.
\ No newline at end of file
coming to FMC card will carry WB clock used by the FPGA module.
doc/manual/ffpg_csr.htm
View file @ c06f91c8
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doc/manual/svec/carrier_csr.htm
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doc/timing-closure-analysis.js
View file @ c06f91c8
// http://wavedrom.com/editor.html
{
signal: [
{name: 'clk', wave: 'PPPP', node: '....', period: 4.99, phase: 0},
{name: 'FPGA-clk-min', wave: 'PPPP', node: 'a...', period: 4.99, phase: -1.478},
{name: 'FPGA-clk-max', wave: 'PPPP', node: 'c...', period: 4.99, phase: -2.514},
{name: 'D-clk-min', wave: 'PPPP', node: '....', period: 4.99, phase: -0.474},
{name: 'D-clk-max', wave: 'PPPP', node: '....', period: 4.99, phase: -0.919},
{name: 'D-data-min', wave: '====', node: '....', period: 4.99, phase: -0.474+0.1},
{name: 'D-data-max', wave: '====', node: '....', period: 4.99, phase: -0.919-0.05},
{name: 'FPGA-data-min', wave: '====', node: '.d..', period: 4.99, phase: -0.474+0.1+0.634},
{name: 'FPGA-data-max', wave: '====', node: '.b..', period: 4.99, phase: -0.919-0.05-0.374},
],
edge: [
'a-~>b ' + Math.round(100*(4.99-1.478+0.919+0.050-0.374), 0.1)/100 + ' ns',
'c~->d ' + Math.round(100*(4.99-2.514+0.474-0.1-0.634), 0.1)/100 + ' ns'
]
}
\ No newline at end of file
// http://wavedrom.com/editor.html
{
signal: [
{name: 'clk', wave: 'PPPP', node: '....', period: 4.99, phase: 0},
{name: 'FPGA-clk-min', wave: 'PPPP', node: 'a...', period: 4.99, phase: -1.478},
{name: 'FPGA-clk-max', wave: 'PPPP', node: 'c...', period: 4.99, phase: -2.514},
{name: 'D-clk-min', wave: 'PPPP', node: '....', period: 4.99, phase: -0.474},
{name: 'D-clk-max', wave: 'PPPP', node: '....', period: 4.99, phase: -0.919},
{name: 'D-data-min', wave: '====', node: '....', period: 4.99, phase: -0.474+0.1},
{name: 'D-data-max', wave: '====', node: '....', period: 4.99, phase: -0.919-0.05},
{name: 'FPGA-data-min', wave: '====', node: '.d..', period: 4.99, phase: -0.474+0.1+0.634},
{name: 'FPGA-data-max', wave: '====', node: '.b..', period: 4.99, phase: -0.919-0.05-0.374},
],
edge: [
'a-~>b ' + Math.round(100*(4.99-1.478+0.919+0.050-0.374), 0.1)/100 + ' ns',
'c~->d ' + Math.round(100*(4.99-2.514+0.474-0.1-0.634), 0.1)/100 + ' ns'
]
}
doc/timing-example.js
View file @ c06f91c8
// http://wavedrom.com/editor.html
{
signal: [
{name: 'CLK IN (400 MHz)', wave: 'PPPPPPPPPPPPPPPPPPPPPPPPPPPPPP', node: '.AB', period: 1, phase: 0},
{node: '.EF.G.H...I'},
{name: 'CLK (200 MHz)', wave: 'PPPPPPPPPPPPPPP', node: '..CD', period: 2, phase: 0},
{name: 'TRIG IN', wave: '0.......1...0..................', node: '...J....K', period: 1, phase: 1},
{name: 'Memory counter', wave: '333333333333333', node: '.l', period: 2, phase: 0, data: ['OVRFLW-1', 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]},
//{name: 'SET Memory', wave: '222222422242222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0]},
//{name: 'RESET Memory', wave: '222222422224222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0]},
{name: 'SET pulse', wave: '0......10..10..', node: '...........M', period: 2, phase: 0},
{name: 'RESET pulse', wave: '0......10...10.', node: '............Q', period: 2, phase: 0},
{name: 'SET pulse (delayed)', wave: '0.......10..10..', node: '........X...N', period: 2, phase: 2-0.5},
{name: 'RESET pulse (delayed)', wave: '0.......10...10.', node: '........Y....R', period: 2, phase: 2-1},
{node: '.......................................S....OPT.V.W...U', period: 0.5},
{name: 'OUT (pulse)', wave: '0............................10..............1....0.........', node: '.............................ZL', period: 0.5, phase: 0},
],
edge: [
'A-E', 'B-F', 'E<->F T',
'G-C', 'H-D', 'G<->H', 'H~I T × (CLOCK_RATIO_M1 + 1)',
'J-l', 'J<->K TRIGGER_LATENCY',
'M-O', 'N-P', 'S->O DELAY_SET', 'O-P', 'T->P',
'Q-V', 'R-W', 'V<->W', 'U-W DELAY_RESET',
'X->Z', 'Y->L'
]
}
\ No newline at end of file
// http://wavedrom.com/editor.html
{
signal: [
{name: 'CLK IN (400 MHz)', wave: 'PPPPPPPPPPPPPPPPPPPPPPPPPPPPPP', node: '.AB', period: 1, phase: 0},
{node: '.EF.G.H...I'},
{name: 'CLK (200 MHz)', wave: 'PPPPPPPPPPPPPPP', node: '..CD', period: 2, phase: 0},
{name: 'TRIG IN', wave: '0.......1...0..................', node: '...J....K', period: 1, phase: 1},
{name: 'Memory counter', wave: '333333333333333', node: '.l', period: 2, phase: 0, data: ['OVRFLW-1', 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]},
//{name: 'SET Memory', wave: '222222422242222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0]},
//{name: 'RESET Memory', wave: '222222422224222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0]},
{name: 'SET pulse', wave: '0......10..10..', node: '...........M', period: 2, phase: 0},
{name: 'RESET pulse', wave: '0......10...10.', node: '............Q', period: 2, phase: 0},
{name: 'SET pulse (delayed)', wave: '0.......10..10..', node: '........X...N', period: 2, phase: 2-0.5},
{name: 'RESET pulse (delayed)', wave: '0.......10...10.', node: '........Y....R', period: 2, phase: 2-1},
{node: '.......................................S....OPT.V.W...U', period: 0.5},
{name: 'OUT (pulse)', wave: '0............................10..............1....0.........', node: '.............................ZL', period: 0.5, phase: 0},
],
edge: [
'A-E', 'B-F', 'E<->F T',
'G-C', 'H-D', 'G<->H', 'H~I T × (CLOCK_RATIO_M1 + 1)',
'J-l', 'J<->K TRIGGER_LATENCY',
'M-O', 'N-P', 'S->O DELAY_SET', 'O-P', 'T->P',
'Q-V', 'R-W', 'V<->W', 'U-W DELAY_RESET',
'X->Z', 'Y->L'
]
}
hdl/ffpg/rtl/Ad9512Control.vhd
View file @ c06f91c8
......@@ -34,7 +34,7 @@
-- 2016-06-21 0.1 Tom Levens
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-07 1.1 Jan Pospisil added OUT4 fine delay configuration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -50,7 +50,7 @@ entity Ad9512Control is
Cfg_i: in std_logic;
Busy_o: out std_logic;
ClockSelection_i: in std_logic; -- 0 - CLK1, 1 - CLK2
ClockRatioMinus1_ib: in unsigned(4 downto 0);
FineDelayEnable_i: in std_logic;
......@@ -90,35 +90,35 @@ architecture syn of Ad9512Control is
------------------------------------------------------------------------
-- Input registers for config
------------------------------------------------------------------------
signal ClockSelection: std_logic := '0';
signal ClockRatioMinus1_b: unsigned(ClockRatioMinus1_ib'range) := to_unsigned(1-1, ClockRatioMinus1_ib'length);
signal FineDelayEnable: std_logic := '0';
signal FineDelay_b: unsigned(FineDelay_ib'range) := to_unsigned(0, FineDelay_ib'length);
signal FineDelayCurrent_b: unsigned(FineDelayCurrent_ib'range) := to_unsigned(0, FineDelayCurrent_ib'length);
signal FineDelayCapacitors_b: unsigned(FineDelayCapacitors_ib'range) := to_unsigned(0, FineDelayCapacitors_ib'length);
------------------------------------------------------------------------
-- AD9512 config registers
------------------------------------------------------------------------
type t_Ad9512Register is record
Address: std_logic_vector(7 downto 0);
Data: std_logic_vector(7 downto 0);
end record;
function f_Ad9512Register2WriteInstruction(Reg: t_Ad9512Register) return std_logic_vector is
variable ZerosToPad: integer := 32-Reg.Address'length-Reg.Data'length;
begin
return std_logic_vector(to_unsigned(0, ZerosToPad)) & Reg.Address & Reg.Data;
end function;
constant c_Ad9512RegisterCount: positive := 17;
type t_Ad9512RegisterFiled is array (integer range <>) of t_Ad9512Register;
signal Ad9512Registers: t_Ad9512RegisterFiled(0 to c_Ad9512RegisterCount-1);
-- calculate cycles according to provided ratio
function f_CreateDivideReg1(ClockRatioMinus1_b: unsigned) return std_logic_vector is
variable LowCycles, HighCycles: unsigned(3 downto 0);
......@@ -135,7 +135,7 @@ architecture syn of Ad9512Control is
return std_logic_vector(LowCycles & HighCycles);
end if;
end function;
-- divider bypass, phase, ...
function f_CreateDivideReg2(ClockRatioMinus1_b: unsigned) return std_logic_vector is
variable PhaseOffset: std_logic_vector(3 downto 0) := "0000";
......@@ -151,11 +151,11 @@ architecture syn of Ad9512Control is
end if;
return Bypass & NoSync & ForceState & StartHL & PhaseOffset;
end function;
------------------------------------------------------------------------
-- SPI core config
------------------------------------------------------------------------
function f_SpiCalcDivider(WbFreq, SpiMaxFreq: positive) return integer is begin
if WbFreq < 2 * SpiMaxFreq then
return 0;
......@@ -163,23 +163,23 @@ architecture syn of Ad9512Control is
return (WbFreq / (SpiMaxFreq * 2));
end if;
end function;
constant c_SpiMaxFrequency: positive := 25e6; -- in Hz
-- ---------------------- ASS
-- / ------------------- IE
-- / / ---------------- LSB
-- / / / ------------- Tx_NEG
-- / / / / ---------- Rx_NEG
-- / / / / / ------- GO_BSY
-- / / / / / /
-- / / / / / /
-- / / / / / / --- CHAR_LEN
-- / / / / / / /
constant c_SpiCtrlReg_b32: -- | | | | | | |
std_logic_vector(13 downto 0) := ("1"&"1"&"0"&"1"&"1"&"0" & X"18");
constant c_SpiGo_b32: -- | | | | | | |
std_logic_vector(13 downto 0) := ("0"&"0"&"0"&"0"&"0"&"1" & X"00");
constant c_SpiSs: std_logic_vector(31 downto 0) := X"00000001";
constant c_SpiDivider: std_logic_vector(31 downto 0) :=
std_logic_vector(to_unsigned(f_SpiCalcDivider(g_ClkFrequency, c_SpiMaxFrequency), 32));
......@@ -392,7 +392,7 @@ begin
mosi_pad_o => SpiAd9512Mosi_o,
miso_pad_i => SpiAd9512Miso_i
);
SpiAd9512Cs_on <= SpiAd9512Cs_n(0);
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/Ad9512Control_tb.vhd
View file @ c06f91c8
......@@ -10,7 +10,7 @@
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
......@@ -29,11 +29,11 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
entity Ad9512Control_tb is
end entity;
......@@ -42,12 +42,12 @@ architecture testbench of Ad9512Control_tb is
constant c_ClkFrequency: positive := 100_000_000;
constant c_ClkPeriod: time := (1 sec)/real(c_ClkFrequency);
signal Clk_ik, Reset_ir, Cfg_i, Busy_o: std_logic := '0';
signal ClockSelection_i: std_logic := '0';
signal ClockRatioMinus1_ib: unsigned(4 downto 0) := to_unsigned(2-1, 5);
signal SpiAd9512Sclk_o, SpiAd9512Mosi_o, SpiAd9512Miso_i, SpiAd9512Cs_on: std_logic := '0';
subtype t_Ratio is Integer range 1 to 32;
procedure f_Tick(ticks: in natural) is begin
......@@ -79,7 +79,7 @@ begin
Clk_ik <= '1';
wait for c_ClkPeriod/2;
end process;
pTest: process is
variable Ratio: t_Ratio;
begin
......@@ -87,7 +87,7 @@ begin
f_Tick(5);
Reset_ir <= '0';
f_Tick(2300);
ClockSelection_i <= '1';
Ratio := 23;
ClockRatioMinus1_ib <= to_unsigned(Ratio-1, ClockRatioMinus1_ib'length);
......@@ -103,4 +103,4 @@ begin
wait;
end process;
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/Ad9512Syncer.vhd
View file @ c06f91c8
......@@ -30,7 +30,7 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -55,7 +55,7 @@ begin
-- AD9512 function pin is set as SYNCB - needs negative pulse > 1.5*T_rfClk
-- (f_rfClk >= 1 MHz) => (1.5*T_rfClk <= 1.5 us)
cAd9512SyncPulseGenerator: entity work.PulseGeneratorTime(syn)
generic map (
g_ClkFrequency => g_ClkFrequency,
......@@ -67,9 +67,9 @@ begin
Signal_i => StartSync_i,
Pulse_o => Pulse
);
GeneratorReset_ra <= Trigger_i and (not Pulse);
pSyncPulseGenerator: process(Clk_ik, GeneratorReset_ra) is begin
if GeneratorReset_ra = '1' then
Ad9512Sync_o <= '0';
......@@ -80,4 +80,4 @@ begin
end if;
end process;
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/ChangeDetector.vhd
View file @ c06f91c8
......@@ -10,17 +10,17 @@ entity ChangeDetector is
end entity;
architecture syn of ChangeDetector is
signal History_b: std_logic_vector(Signal_ib'range) := (others => '0');
begin
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History_b <= Signal_ib;
end if;
end process;
pDetection: process (Signal_ib, History_b) is
variable Result: std_logic;
begin
......@@ -30,5 +30,5 @@ begin
end loop;
Change_o <= Result;
end process;
end architecture;
hdl/ffpg/rtl/Counter.vhd
View file @ c06f91c8
......@@ -55,7 +55,7 @@ architecture syn of Counter is
--! actual value of the counter
signal Value_b: unsigned(g_Width-1 downto 0) := (others => '0');
begin
--! synchronous counter with synchronous reset
......@@ -77,9 +77,9 @@ begin
end process pCounter;
Value_ob <= Value_b;
Overflow_o <=
'1' when Value_b = c_StopValue else
'0';
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/CounterLength.vhd
View file @ c06f91c8
......@@ -49,10 +49,10 @@ architecture syn of CounterLength is
end loop;
return i;
end function;
--! width of the vector needed for storing actual counter value
constant c_Width: natural := f_log2(g_Length);
begin
cCounter: entity work.Counter(syn)
......@@ -70,4 +70,4 @@ begin
Value_ob => open
);
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/Counter_tb.vhd
View file @ c06f91c8
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
......@@ -12,10 +12,10 @@ architecture testbench_width of Counter_tb is
constant c_ClkPeriod: time := 50 ns;
constant c_Width: natural := 8;
signal Clk, Reset, Enable, Overflow: std_logic;
signal Value_b: unsigned(c_Width-1 downto 0);
procedure f_Tick(ticks: in natural) is begin
wait for ticks * c_ClkPeriod;
end procedure;
......@@ -42,7 +42,7 @@ begin
Clk <= '1';
wait for c_ClkPeriod/2;
end process;
pTest: process is begin
Reset <= '1';
Enable <= '0';
......@@ -66,7 +66,7 @@ begin
report "Bad VALUE!"
severity failure;
end loop;
f_Tick(1);
assert Overflow = '0'
report "OVERFLOW asserted at the end!"
......@@ -102,7 +102,7 @@ architecture testbench_length of Counter_tb is
constant c_ClkPeriod: time := 50 ns;
constant c_Width: natural := 5;
constant c_Length: natural := 2**c_Width -0; -- can be minus something to test more cases
signal Clk, Reset, Enable, Overflow: std_logic;
procedure f_Tick(ticks: in natural) is begin
......@@ -128,7 +128,7 @@ begin
Clk <= '1';
wait for c_ClkPeriod/2;
end process;
pTest: process is begin
Reset <= '1';
Enable <= '0';
......@@ -146,7 +146,7 @@ begin
report "OVERFLOW asserted!"
severity failure;
end loop;
f_Tick(1);
assert Overflow = '0'
report "OVERFLOW asserted at the end!"
......@@ -166,4 +166,4 @@ begin
wait;
end process;
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/DacsController.vhd
View file @ c06f91c8
......@@ -29,7 +29,7 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -90,14 +90,14 @@ architecture syn of DacsController is
signal Reset_nr: std_logic;
signal TriggerDacEn, VcxoDacEn: std_logic;
signal TriggerBusy, VcxoBusy: std_logic;
begin
Reset_nr <= not Reset_ir;
TriggerDacEn <= TriggerLoad_i and not TriggerBusy;
VcxoDacEn <= VcxoLoad_i and not VcxoBusy;
cTriggerDac: entity work.gc_serial_dac(syn)
generic map (
g_num_data_bits => 16,
......@@ -137,7 +137,7 @@ begin
dac_sdata_o => VcxoDac_o.SerialData,
busy_o => VcxoBusy
);
TriggerBusy_o <= TriggerBusy;
VcxoBusy_o <= VcxoBusy;
......
hdl/ffpg/rtl/Delay.vhd
View file @ c06f91c8
......@@ -2,76 +2,76 @@ library ieee;
use ieee.std_logic_1164.all;
entity Delay is
generic (
g_Width: integer := 1;
g_Delay: integer := 5;
g_AsyncRegUsed: string := "FALSE"
);
port (
Clk_ik: in std_logic;
Data_ib: in std_logic_vector(g_Width-1 downto 0);
Data_ob: out std_logic_vector(g_Width-1 downto 0)
);
generic (
g_Width: integer := 1;
g_Delay: integer := 5;
g_AsyncRegUsed: string := "FALSE"
);
port (
Clk_ik: in std_logic;
Data_ib: in std_logic_vector(g_Width-1 downto 0);
Data_ob: out std_logic_vector(g_Width-1 downto 0)
);
end entity;
architecture syn of Delay is
attribute ASYNC_REG: string;
attribute ASYNC_REG: string;
signal ShiftRegister: std_logic_vector((g_Width*(g_Delay+1))-1 downto g_Width-1) := (others => '0');
signal ShiftRegister: std_logic_vector((g_Width*(g_Delay+1))-1 downto g_Width-1) := (others => '0');
attribute ASYNC_REG of ShiftRegister: signal is g_AsyncRegUsed;
attribute ASYNC_REG of ShiftRegister: signal is g_AsyncRegUsed;
begin
-- ShiftRegister(g_Width-1 downto 0) <= Data_ib;
gDelay: if g_Delay > 0 generate
pDelay: process (Clk_ik) begin
if rising_edge(Clk_ik) then
for i in 1 to g_Delay loop
if i = 1 then
ShiftRegister((g_Width*(i+1))-1 downto g_Width*i) <= Data_ib;
else
ShiftRegister((g_Width*(i+1))-1 downto g_Width*i) <= ShiftRegister((g_Width*i)-1 downto g_Width*(i-1));
end if;
end loop;
end if;
end process pDelay;
end generate gDelay;
gOutputWithDelay: if g_Delay > 0 generate
Data_ob <= ShiftRegister((g_Width*(g_Delay+1))-1 downto g_Width*g_Delay);
end generate;
gOutputWithoutDelay: if g_Delay = 0 generate
Data_ob <= Data_ib;
end generate;
-- ShiftRegister(g_Width-1 downto 0) <= Data_ib;
gDelay: if g_Delay > 0 generate
pDelay: process (Clk_ik) begin
if rising_edge(Clk_ik) then
for i in 1 to g_Delay loop
if i = 1 then
ShiftRegister((g_Width*(i+1))-1 downto g_Width*i) <= Data_ib;
else
ShiftRegister((g_Width*(i+1))-1 downto g_Width*i) <= ShiftRegister((g_Width*i)-1 downto g_Width*(i-1));
end if;
end loop;
end if;
end process pDelay;
end generate gDelay;
gOutputWithDelay: if g_Delay > 0 generate
Data_ob <= ShiftRegister((g_Width*(g_Delay+1))-1 downto g_Width*g_Delay);
end generate;
gOutputWithoutDelay: if g_Delay = 0 generate
Data_ob <= Data_ib;
end generate;
end architecture;
architecture notWorking of Delay is
attribute ASYNC_REG: string;
attribute ASYNC_REG: string;
signal ShiftRegister: std_logic_vector((g_Width*(g_Delay+1))-1 downto 0);
signal ShiftRegister: std_logic_vector((g_Width*(g_Delay+1))-1 downto 0);
attribute ASYNC_REG of ShiftRegister: signal is g_AsyncRegUsed;
attribute ASYNC_REG of ShiftRegister: signal is g_AsyncRegUsed;
begin
ShiftRegister(g_Width-1 downto 0) <= Data_ib;
gDelay: if g_Delay > 0 generate
pDelay: process (Clk_ik) begin
if rising_edge(Clk_ik) then
for i in 1 to g_Delay loop
ShiftRegister((g_Width*(i+1))-1 downto g_Width*i) <= ShiftRegister((g_Width*i)-1 downto g_Width*(i-1));
end loop;
end if;
end process pDelay;
end generate gDelay;
Data_ob <= ShiftRegister((g_Width*(g_Delay+1))-1 downto g_Width*g_Delay);
ShiftRegister(g_Width-1 downto 0) <= Data_ib;
gDelay: if g_Delay > 0 generate
pDelay: process (Clk_ik) begin
if rising_edge(Clk_ik) then
for i in 1 to g_Delay loop
ShiftRegister((g_Width*(i+1))-1 downto g_Width*i) <= ShiftRegister((g_Width*i)-1 downto g_Width*(i-1));
end loop;
end if;
end process pDelay;
end generate gDelay;
Data_ob <= ShiftRegister((g_Width*(g_Delay+1))-1 downto g_Width*g_Delay);
end architecture;
hdl/ffpg/rtl/DelayController.vhd
View file @ c06f91c8
......@@ -29,7 +29,7 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -114,7 +114,7 @@ begin
Signal_i => StartConfiguration,
Pulse_o => LoadPulse
);
Ch1SetLe_on <=
'0' when (ActiveOutput = e_Ch1Set) and LoadPulse = '1' else
'1';
......
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
View file @ c06f91c8
......@@ -31,7 +31,7 @@
-- Date Version Author Comment
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-07 1.1 Jan Pospisil forced set/reset pulse registers to IOB
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -73,7 +73,7 @@ architecture syn of DelayedPulseGenerator is
constant c_MemLatency: integer := 2+1;
-- +1 for memory output registers implemented here
-- for memory output registers
signal SetMemData_b32: unsigned(SetMemData_ib32'range) := (others => '0');
signal ResMemData_b32: unsigned(ResMemData_ib32'range) := (others => '0');
......@@ -83,23 +83,23 @@ architecture syn of DelayedPulseGenerator is
signal GenerationEnable: std_logic;
signal OutputEnable: std_logic;
signal AddressEnableCounterOverflow: std_logic;
signal AddressEnableCounterSetValue: unsigned(TriggerLatency_ib16'range);
signal AddressCounterReset: std_logic := '0';
signal AddressCounterResetOrReset: std_logic;
signal AddressCounterSetValue: unsigned(TriggerLatency_ib16'range);
signal AddressCounterValue: unsigned(SetMemAddress_ob11'range);
signal StreamReset: std_logic := '0';
signal StreamResetOrReset: std_logic;
signal StreamPosition: unsigned(Overflow_ib16'range);
signal BitCounterOverflow, LoadShiftRegister: std_logic;
signal SetStream, ResetStream: std_logic;
begin
-- memory output registers
......@@ -144,7 +144,7 @@ begin
end if;
end if;
end process;
AddressCounterResetOrReset <= AddressCounterReset or Reset_ir;
AddressEnableCounterSetValue <= TriggerLatencyPlusTwo + c_MemLatency;
cAddressEnableCounter: entity work.Counter(syn)
......@@ -175,13 +175,13 @@ begin
Overflow_o => open,
Value_ob => AddressCounterValue
);
SetMemAddress_ob11 <= AddressCounterValue;
ResMemAddress_ob11 <= AddressCounterValue;
SetMemReadStrobe_o <= '0'; -- this is not connected anywhere!!
ResMemReadStrobe_o <= '0'; -- this is not connected anywhere!!
-- for better timing
pStreamResetReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
......@@ -192,7 +192,7 @@ begin
end if;
end if;
end process;
StreamResetOrReset <= StreamReset or Reset_ir;
cStreamCounter: entity work.Counter(syn)
......@@ -208,7 +208,7 @@ begin
Overflow_o => open,
Value_ob => StreamPosition
);
cBitCounter: entity work.Counter(syn)
generic map (
g_Width => 5
......@@ -222,9 +222,9 @@ begin
Overflow_o => BitCounterOverflow,
Value_ob => open
);
LoadShiftRegister <= BitCounterOverflow or StreamReset;
cShiftRegisterSet: entity work.ShiftRegister(right)
generic map (
g_Width => SetMemData_b32'length
......@@ -239,7 +239,7 @@ begin
ShiftEnable_i => GenerationEnable,
LoadEnable_i => LoadShiftRegister
);
cShiftRegisterReset: entity work.ShiftRegister(right)
generic map (
g_Width => ResMemData_b32'length
......@@ -254,7 +254,7 @@ begin
ShiftEnable_i => GenerationEnable,
LoadEnable_i => LoadShiftRegister
);
pOutputRegs: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if OutputEnable = '1' then
......@@ -266,5 +266,5 @@ begin
end if;
end if;
end process;
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
View file @ c06f91c8
......@@ -32,7 +32,7 @@
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-05 1.1 Jan Pospisil Independent Trigger Latency for the two
-- channels (issue 1389)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -129,18 +129,18 @@ begin
Data_ib(0) => Trigger_i,
Data_ob(0) => TriggerRf
);
cTriggerEdgeDetector: entity work.EdgeDetector(rising)
port map (
Clk_ik => ClkRf_ik,
Signal_i => TriggerRf,
Edge_o => TriggerRfPulse
);
-- Overflow
Overflow_b_slv <= std_logic_vector(Overflow_ib16);
cOverflowSyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
......@@ -150,13 +150,13 @@ begin
Data_ob => OverflowRf_b_slv,
Load_o => open
);
OverflowRf_b <= unsigned(OverflowRf_b_slv);
-- Ch1TriggerLatency
Ch1TriggerLatency_b_slv <= std_logic_vector(Ch1TriggerLatency_ib16);
cCh1TriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
......@@ -166,13 +166,13 @@ begin
Data_ob => Ch1TriggerLatencyRf_b_slv,
Load_o => open
);
Ch1TriggerLatencyRf_b <= unsigned(Ch1TriggerLatencyRf_b_slv);
-- Ch2TriggerLatency
Ch2TriggerLatency_b_slv <= std_logic_vector(Ch2TriggerLatency_ib16);
cCh2TriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
......@@ -182,20 +182,20 @@ begin
Data_ob => Ch2TriggerLatencyRf_b_slv,
Load_o => open
);
Ch2TriggerLatencyRf_b <= unsigned(Ch2TriggerLatencyRf_b_slv);
-- Ch1Mode
Ch1Mode_slv <= f_ModeToSlv(Ch1Mode_i);
cCh1ModeChange: entity work.ChangeDetector(syn)
port map (
Clk_ik => Clk_ik,
Signal_ib => Ch1Mode_slv,
Change_o => Ch1ModeLoad
);
cCh1ModeSyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
......@@ -205,20 +205,20 @@ begin
Data_ob => Ch1ModeRf_slv,
Load_o => Ch1ModeLoadRf
);
Ch1ModeRf <= f_SlvToMode(Ch1ModeRf_slv);
-- Ch2Mode
Ch2Mode_slv <= f_ModeToSlv(Ch2Mode_i);
cCh2ModeChange: entity work.ChangeDetector(syn)
port map (
Clk_ik => Clk_ik,
Signal_ib => Ch2Mode_slv,
Change_o => Ch2ModeLoad
);
cCh2ModeSyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
......@@ -228,7 +228,7 @@ begin
Data_ob => Ch2ModeRf_slv,
Load_o => Ch2ModeLoadRf
);
Ch2ModeRf <= f_SlvToMode(Ch2ModeRf_slv);
----------------------------------
......@@ -305,4 +305,4 @@ begin
Data_ob(0) => Ch2Running_o
);
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
View file @ c06f91c8
......@@ -30,7 +30,7 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -65,23 +65,23 @@ architecture syn of Fsm is
s_Generating,
s_Outputting
);
function f_State2Unsigned (State: t_State) return unsigned is begin
return to_unsigned(t_State'pos(State), 3);
end function;
constant c_ResetState: t_State := s_Stop;
signal State: t_State := c_ResetState;
begin
pFsmTransitions: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
State <= c_ResetState;
else
State <= State;
pFsmTransitions: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
State <= c_ResetState;
else
State <= State;
if ModeLoad_i = '1' then
-- global paths
if Mode_i = e_ModeStop then
......@@ -110,10 +110,10 @@ begin
State <= c_ResetState;
end case;
end if;
end if;
end if;
end process;
end if;
end if;
end process;
pFsmOutputs: process (State) is begin
Running_o <= '0';
OutputEnable_o <= '0';
......@@ -131,7 +131,7 @@ begin
when others => null;
end case;
end process;
State_o <= f_State2Unsigned(State);
end architecture;
\ No newline at end of file
end architecture;
hdl/ffpg/rtl/EdgeDetector.vhd
View file @ c06f91c8
......@@ -2,57 +2,57 @@ library ieee;
use ieee.std_logic_1164.all;
entity EdgeDetector is
port (
Clk_ik: in std_logic;
Signal_i: in std_logic;
Edge_o: out std_logic
);
port (
Clk_ik: in std_logic;
Signal_i: in std_logic;
Edge_o: out std_logic
);
end entity;
architecture rising of EdgeDetector is
signal History: std_logic := '0';
signal History: std_logic := '0';
begin
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History <= Signal_i;
end if;
end process;
Edge_o <= Signal_i and not History;
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History <= Signal_i;
end if;
end process;
Edge_o <= Signal_i and not History;
end architecture;
architecture falling of EdgeDetector is
signal History: std_logic := '0';
signal History: std_logic := '0';
begin
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History <= Signal_i;
end if;
end process;
Edge_o <= not Signal_i and History;
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History <= Signal_i;
end if;
end process;
Edge_o <= not Signal_i and History;
end architecture;
architecture both of EdgeDetector is
signal History: std_logic := '0';
signal History: std_logic := '0';
begin
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History <= Signal_i;
end if;
end process;
Edge_o <= Signal_i xor History;
pDelay: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
History <= Signal_i;
end if;
end process;
Edge_o <= Signal_i xor History;
end architecture;
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hdl/ffpg/rtl/Manifest.py
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......@@ -5,5 +5,5 @@ files = [
"FfpgCorePkg.vhd",
"../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
]
modules = { "local" : ["../../ip_cores/wishbone-gen/lib"]}
hdl/ffpg/rtl/Reg.vhd
View file @ c06f91c8
......@@ -11,16 +11,16 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Reg is
generic (
g_ResetValue: natural := 0
);
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Data_ib: in std_logic_vector;
Enable_i: in std_logic;
Data_ob: out std_logic_vector
);
generic (
g_ResetValue: natural := 0
);
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Data_ib: in std_logic_vector;
Enable_i: in std_logic;
Data_ob: out std_logic_vector
);
end entity;
architecture syn of Reg is
......@@ -30,16 +30,16 @@ architecture syn of Reg is
begin
pReg: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
Data_b <= c_ResetValue;
elsif Enable_i = '1' then
Data_b <= Data_ib;
end if;
end if;
end process;
pReg: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
Data_b <= c_ResetValue;
elsif Enable_i = '1' then
Data_b <= Data_ib;
end if;
end if;
end process;
Data_ob <= Data_b;
end architecture;
hdl/ffpg/rtl/RegSyncer.vhd
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hdl/ffpg/rtl/ResetSyncer.vhd
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......@@ -56,7 +56,7 @@ begin
ShiftRegister2 <= ShiftRegister1;
end if;
end process;
Reset_or <= ShiftRegister2;
end architecture;
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