- 24 Jul, 2020 4 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 04 Sep, 2019 10 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Note: P2L DMA already supported this for DMA writes.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 03 Sep, 2019 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 30 Aug, 2019 1 commit
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Tristan Gingold authored
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- 29 Aug, 2019 2 commits
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Tristan Gingold authored
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Dimitris Lampridis authored
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- 28 Aug, 2019 1 commit
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Tristan Gingold authored
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- 23 Aug, 2019 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 08 Aug, 2019 4 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 07 Aug, 2019 1 commit
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Dimitris Lampridis authored
[hdl] fix bug in new dma_controller where the DMA status was not properly exposed through the WB registers
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- 06 Aug, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 05 Aug, 2019 1 commit
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Dimitris Lampridis authored
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- 01 Aug, 2019 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 17 Jul, 2019 2 commits
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Tristan Gingold authored
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Dimitris Lampridis authored
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- 16 Jul, 2019 1 commit
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Dimitris Lampridis authored
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- 20 May, 2019 1 commit
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Dimitris Lampridis authored
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- 06 May, 2019 1 commit
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Dimitris Lampridis authored
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- 30 Apr, 2019 1 commit
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Dimitris Lampridis authored
Following up on 6c4dca2c, this commit fixes one issue related to resets and performs further reset and clock-domain crossing (CDC) cleanup. Important changes include: 1. Make sure that all dual async fifos are reset on both sides. This solves an issue with soft resets causing the host PC to hang. 2. Remove c_RST_ACTIVE constant to make the code simpler. 3. Remove reset from many signals (in particular from wide, data signals) that do not need to be reset. This helps with meeting timing wrt reset distribution. 4. Remove synchronizers from p2l deserializers, the SERDES outputs are already synced to the FPGA clock.
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- 26 Apr, 2019 1 commit
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Dimitris Lampridis authored
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