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Gennum GN4124 core
Commits
9e43b261
Commit
9e43b261
authored
Sep 03, 2019
by
Tristan Gingold
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dma_controller: renames keep signals to ease constraints.
parent
542aa7ea
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30 additions
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26 deletions
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-26
dma_controller.vhd
hdl/rtl/dma_controller.vhd
+30
-26
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hdl/rtl/dma_controller.vhd
View file @
9e43b261
...
...
@@ -96,14 +96,14 @@ architecture arch of dma_controller is
signal
dma_ctrl_start
:
std_logic
;
signal
dma_ctrl_abort
:
std_logic
;
signal
dma_ctrl_wr
:
std_logic
;
signal
dma_
cstart
:
std_logic_vector
(
31
downto
0
);
signal
dma_
hstartl
:
std_logic_vector
(
31
downto
0
);
signal
dma_
hstarth
:
std_logic_vector
(
31
downto
0
);
signal
dma_
len
:
std_logic_vector
(
31
downto
0
);
signal
dma_
nextl
:
std_logic_vector
(
31
downto
0
);
signal
dma_
nexth
:
std_logic_vector
(
31
downto
0
);
signal
dma_a
ttrib_chain
:
std_logic
;
signal
dma_a
ttrib_dir
:
std_logic
;
signal
dma_
async_cstart
:
std_logic_vector
(
31
downto
0
);
signal
dma_
async_hstartl
:
std_logic_vector
(
31
downto
0
);
signal
dma_
async_hstarth
:
std_logic_vector
(
31
downto
0
);
signal
dma_
async_len
:
std_logic_vector
(
31
downto
0
);
signal
dma_
async_nextl
:
std_logic_vector
(
31
downto
0
);
signal
dma_
async_nexth
:
std_logic_vector
(
31
downto
0
);
signal
dma_a
sync_attrib_chain
:
std_logic
;
signal
dma_a
sync_attrib_dir
:
std_logic
;
signal
dma_stat_irq_i_wb
:
std_logic
;
signal
dma_stat_irq_o_wb
:
std_logic
;
signal
dma_stat_status_wb
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -133,9 +133,13 @@ architecture arch of dma_controller is
signal
dma_stat_reg
:
std_logic_vector
(
1
downto
0
);
signal
dma_irq_reg
:
std_logic
;
-- This signals come from registers clocked by the dma_reg_clk but read by registers clocked
-- by sys_clk. Synchronization is safe because they are read many clocks later (when a DMA
-- is started), assuming the user doesn't modify them...
-- To relax timing constraints, they share a common prefix 'dma_async_'.
attribute
keep
:
string
;
attribute
keep
of
dma_
cstart
,
dma_hstartl
,
dma_hstarth
,
dma
_len
,
dma_
nextl
,
dma_nexth
,
dma_attrib_chain
,
dma
_attrib_dir
:
signal
is
"true"
;
attribute
keep
of
dma_
async_cstart
,
dma_async_hstartl
,
dma_async_hstarth
,
dma_async
_len
,
dma_
async_nextl
,
dma_async_nexth
,
dma_async_attrib_chain
,
dma_async
_attrib_dir
:
signal
is
"true"
;
begin
...
...
@@ -170,14 +174,14 @@ begin
stat_wack_i
=>
dma_stat_wack_wb
,
stat_rd_o
=>
dma_stat_rd_wb
,
stat_rack_i
=>
dma_stat_rack_wb
,
cstart_o
=>
dma_cstart
,
hstartl_o
=>
dma_hstartl
,
hstarth_o
=>
dma_hstarth
,
len_o
=>
dma_len
,
nextl_o
=>
dma_nextl
,
nexth_o
=>
dma_nexth
,
attrib_chain_o
=>
dma_attrib_chain
,
attrib_dir_o
=>
dma_attrib_dir
,
cstart_o
=>
dma_
async_
cstart
,
hstartl_o
=>
dma_
async_
hstartl
,
hstarth_o
=>
dma_
async_
hstarth
,
len_o
=>
dma_
async_
len
,
nextl_o
=>
dma_
async_
nextl
,
nexth_o
=>
dma_
async_
nexth
,
attrib_chain_o
=>
dma_a
sync_a
ttrib_chain
,
attrib_dir_o
=>
dma_a
sync_a
ttrib_dir
,
cur_cstart_i
=>
dma_cstart_reg
,
cur_hstartl_i
=>
dma_hstartl_reg
,
cur_hstarth_i
=>
dma_hstarth_reg
,
...
...
@@ -274,14 +278,14 @@ begin
if
(
dma_ctrl_wr
and
dma_ctrl_start
)
=
'1'
then
-- Capture parameters
-- All these inputs registers are synchronized on the start pulse.
dma_cstart_reg
<=
dma_cstart
;
dma_hstartl_reg
<=
dma_hstartl
;
dma_hstarth_reg
<=
dma_hstarth
;
dma_len_reg
<=
dma_len
;
dma_nextl_reg
<=
dma_nextl
;
dma_nexth_reg
<=
dma_nexth
;
dma_attrib_chain_reg
<=
dma_attrib_chain
;
dma_attrib_dir_reg
<=
dma_attrib_dir
;
dma_cstart_reg
<=
dma_
async_
cstart
;
dma_hstartl_reg
<=
dma_
async_
hstartl
;
dma_hstarth_reg
<=
dma_
async_
hstarth
;
dma_len_reg
<=
dma_
async_
len
;
dma_nextl_reg
<=
dma_
async_
nextl
;
dma_nexth_reg
<=
dma_
async_
nexth
;
dma_attrib_chain_reg
<=
dma_a
sync_a
ttrib_chain
;
dma_attrib_dir_reg
<=
dma_a
sync_a
ttrib_dir
;
dma_ctrl_byte_swap_reg
<=
dma_ctrl_byte_swap
;
-- Starts a new transfer
dma_ctrl_current_state
<=
DMA_START_TRANSFER
;
...
...
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