Commit d4e66a5c authored by Dimitris Lampridis's avatar Dimitris Lampridis

[sim] update testbench

parent 9436c05c
......@@ -185,7 +185,7 @@ module main;
$write("PASS\n");
$write("Test %0d/%0d: 32 reads over DMA, abort after first read: ",
$write("Test %0d/%0d: 128B read over DMA, abort after first read: ",
ntest++, tests);
if (dma_irq != 1'b0)
......@@ -215,7 +215,7 @@ module main;
$write("PASS\n");
$write("Test %0d/%0d: 2x32 chained reads over DMA: ",
$write("Test %0d/%0d: 2x128B chained reads over DMA: ",
ntest++, tests);
// Setup DMA chain info in BFM memory
......@@ -286,7 +286,7 @@ module main;
// Check all four byte swap settings
// ---------------------------------
for (int i = 0; i < 4; i++) begin
$write("Test %0d/%0d: 16KB reads over DMA (byte swap = %0d): ",
$write("Test %0d/%0d: 64KB read over DMA (byte swap = %0d): ",
ntest++, tests, i);
// Restart
......@@ -303,7 +303,6 @@ module main;
for (addr = 'h00; addr < 'h1000; addr += 1)
begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
$write("ex: %x", expected);
if (i == 1)
expected = {<<8{expected}};
else if (i == 2)
......@@ -327,5 +326,6 @@ module main;
$display("Simulation PASSED");
$finish;
end
end // initial begin
endmodule // main
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