[hdl] update example testbench to also test DMA aborts

5e368b58 · Dimitris Lampridis · 352c0db5 · 5e368b58
Commit 5e368b58 authored Aug 06, 2019 by Dimitris Lampridis
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main.sv hdl/sim/example_tb/main.sv +114 -79

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--- a/hdl/sim/example_tb/main.sv
+++ b/hdl/sim/example_tb/main.sv
@@ -55,44 +55,44 @@ module main;

   xwb_gn4124_core
     DUT (
-	  .rst_n_a_i          (i_gn4124.rst_n),
-	  .p2l_clk_p_i        (i_gn4124.p2l_clk_p),
-	  .p2l_clk_n_i        (i_gn4124.p2l_clk_n),
-	  .p2l_data_i         (i_gn4124.p2l_data),
-	  .p2l_dframe_i       (i_gn4124.p2l_dframe),
-	  .p2l_valid_i        (i_gn4124.p2l_valid),
-	  .p2l_rdy_o          (i_gn4124.p2l_rdy),
-	  .p_wr_req_i         (i_gn4124.p_wr_req),
-	  .p_wr_rdy_o         (i_gn4124.p_wr_rdy),
-	  .rx_error_o         (i_gn4124.rx_error),
-	  .vc_rdy_i           (i_gn4124.vc_rdy),
-	  .l2p_clk_p_o        (i_gn4124.l2p_clk_p),
-	  .l2p_clk_n_o        (i_gn4124.l2p_clk_n),
-	  .l2p_data_o         (i_gn4124.l2p_data),
-	  .l2p_dframe_o       (i_gn4124.l2p_dframe),
-	  .l2p_valid_o        (i_gn4124.l2p_valid),
-	  .l2p_edb_o          (i_gn4124.l2p_edb),
-	  .l2p_rdy_i          (i_gn4124.l2p_rdy),
-	  .l_wr_rdy_i         (i_gn4124.l_wr_rdy),
-	  .p_rd_d_rdy_i       (i_gn4124.p_rd_d_rdy),
-	  .tx_error_i         (i_gn4124.tx_error),
-	  .dma_irq_o          (dma_irq),
-	  .irq_p_i            (1'b0),
-	  .irq_p_o            (gn4124_irq),
-	  .status_o           (),
-	  .wb_master_clk_i    (clk_125m),
-	  .wb_master_rst_n_i  (rst_125m_n),
-	  .wb_master_i        (wb_in),
-	  .wb_master_o        (wb_out),
-	  .wb_dma_cfg_clk_i   (clk_125m),
-	  .wb_dma_cfg_rst_n_i (rst_125m_n),
-	  .wb_dma_cfg_i       (wb_out),
-	  .wb_dma_cfg_o       (wb_in),
-	  .wb_dma_dat_clk_i   (clk_125m),
-	  .wb_dma_dat_rst_n_i (rst_125m_n),
-	  .wb_dma_dat_i       (wb_dma_in),
-	  .wb_dma_dat_o       (wb_dma_out)
-	  );
+          .rst_n_a_i          (i_gn4124.rst_n),
+          .p2l_clk_p_i        (i_gn4124.p2l_clk_p),
+          .p2l_clk_n_i        (i_gn4124.p2l_clk_n),
+          .p2l_data_i         (i_gn4124.p2l_data),
+          .p2l_dframe_i       (i_gn4124.p2l_dframe),
+          .p2l_valid_i        (i_gn4124.p2l_valid),
+          .p2l_rdy_o          (i_gn4124.p2l_rdy),
+          .p_wr_req_i         (i_gn4124.p_wr_req),
+          .p_wr_rdy_o         (i_gn4124.p_wr_rdy),
+          .rx_error_o         (i_gn4124.rx_error),
+          .vc_rdy_i           (i_gn4124.vc_rdy),
+          .l2p_clk_p_o        (i_gn4124.l2p_clk_p),
+          .l2p_clk_n_o        (i_gn4124.l2p_clk_n),
+          .l2p_data_o         (i_gn4124.l2p_data),
+          .l2p_dframe_o       (i_gn4124.l2p_dframe),
+          .l2p_valid_o        (i_gn4124.l2p_valid),
+          .l2p_edb_o          (i_gn4124.l2p_edb),
+          .l2p_rdy_i          (i_gn4124.l2p_rdy),
+          .l_wr_rdy_i         (i_gn4124.l_wr_rdy),
+          .p_rd_d_rdy_i       (i_gn4124.p_rd_d_rdy),
+          .tx_error_i         (i_gn4124.tx_error),
+          .dma_irq_o          (dma_irq),
+          .irq_p_i            (1'b0),
+          .irq_p_o            (gn4124_irq),
+          .status_o           (),
+          .wb_master_clk_i    (clk_125m),
+          .wb_master_rst_n_i  (rst_125m_n),
+          .wb_master_i        (wb_in),
+          .wb_master_o        (wb_out),
+          .wb_dma_cfg_clk_i   (clk_125m),
+          .wb_dma_cfg_rst_n_i (rst_125m_n),
+          .wb_dma_cfg_i       (wb_out),
+          .wb_dma_cfg_o       (wb_in),
+          .wb_dma_dat_clk_i   (clk_125m),
+          .wb_dma_dat_rst_n_i (rst_125m_n),
+          .wb_dma_dat_i       (wb_dma_in),
+          .wb_dma_dat_o       (wb_dma_out)
+          );

   xwb_dpram #
     (
@@ -104,26 +104,24 @@ module main;
      .g_slave2_granularity    (1)
      )
   MEM (
-	.rst_n_i   (1'b1),
-	.clk_sys_i (clk_125m),
-	.slave1_i  (wb_dma_out),
-	.slave1_o  (wb_dma_in),
-	.slave2_i  (wb_mem_out),
-	.slave2_o  (wb_mem_in)
-	);
+        .rst_n_i   (1'b1),
+        .clk_sys_i (clk_125m),
+        .slave1_i  (wb_dma_out),
+        .slave1_o  (wb_dma_in),
+        .slave2_i  (wb_mem_out),
+        .slave2_o  (wb_mem_in)
+        );

   CBusAccessor acc;

   task val_check(string name, uint64_t addr, val, expected);
      if (val != expected)
-	begin
-	   $display();
-	   $display("Simulation FAILED");
-	   $fatal(1, "%s error at address 0x%.2x. Expected 0x%.8x, got 0x%.8x",
-		  name, addr, expected, val);
-	end
-      $display("%s at address 0x%.2x: 0x%.8x [OK]",
-	       name, addr, val);
+        begin
+           $display();
+           $display("Simulation FAILED");
+           $fatal(1, "%s error at address 0x%.2x. Expected 0x%.8x, got 0x%.8x",
+                  name, addr, expected, val);
+        end
   endtask // val_check

   task reg_check(uint64_t addr, expected);
@@ -144,6 +142,8 @@ module main;

      @(posedge clk_125m);

+      $write("Test 1/3: simple read/write accesses over Wishbone: ");
+
      // Verify simple read/writes over wishbone
      reg_check('h0, 'h0);

@@ -155,14 +155,20 @@ module main;

      // Reset all DMA config registers
      for (addr = 'h00; addr <= 'h20; addr += 4)
-	begin
-	   acc.write(addr, 'h0);
-	end
+        begin
+           acc.write(addr, 'h0);
+        end
+
+      $write("PASS\n");
+
+      $write("Test 2/3: 32 reads over DMA, abort after first read: ");

      // Perform 32 reads over DMA
-	  reg_check('h00, 'h00000000);
-	  if (dma_irq != 1'b0)
-	  	$fatal(1, "dma irq should be 0");
+      reg_check('h00, 'h00000000);
+
+      if (dma_irq != 1'b0)
+        $fatal(1, "dma irq should be 0");
+
      acc.write('h14, 'h80); // count
      acc.write('h00, 'h01); // start

@@ -170,27 +176,56 @@ module main;
      @(posedge i_gn4124.l2p_valid); // skip header
      @(posedge i_gn4124.l2p_valid);

+      expected = 64'h8000001f;
+      val = i_gn4124.l2p_data;
+      @(posedge i_gn4124.l2p_clk_n);
+      val |= i_gn4124.l2p_data << 16;
+      val_check("DMA read-back", 'h20, val, expected);
+
+      repeat(2) @(posedge clk_125m);
+
+      // Test abort feature
+      acc.write('h00, 'h02);
+      reg_check('h04, 'h03);
+      acc.write('h00, 'h00);
+
+      repeat(2) @(posedge clk_125m);
+
+      $write("PASS\n");
+
+      $write("Test 3/3: 32 reads over DMA: ");
+
+      // Restart
+      acc.write('h14, 'h80); // count
+      acc.write('h00, 'h01); // start
+
+      @(posedge i_gn4124.l2p_valid); // skip header
+      @(posedge i_gn4124.l2p_valid);
+
      for (addr = 'h20; addr > 'h00; addr -= 1)
-	begin
-	   expected = 64'h80000000 + addr - 1;
-	   val = i_gn4124.l2p_data;
-	   @(posedge i_gn4124.l2p_clk_n);
-	   val |= i_gn4124.l2p_data << 16;
-	   val_check("DMA read-back", 'h20-addr, val, expected);
-	   @(posedge i_gn4124.l2p_clk_p);
-	end
-
-	repeat(4) @(posedge clk_125m);
-
-    //  Check irq status
-    reg_check('h04, 'h04);
-    if (dma_irq != 1'b1)
-    	$fatal(1, "dma irq should be 1");
-	// clear irq
-    acc.write('h04, 'h04);
-    reg_check('h04, 'h00);
-    if (dma_irq != 1'b0)
-    	$fatal(1, "dma irq should be 0");
+        begin
+           expected = 64'h80000000 + addr - 1;
+           val = i_gn4124.l2p_data;
+           @(posedge i_gn4124.l2p_clk_n);
+           val |= i_gn4124.l2p_data << 16;
+           val_check("DMA read-back", 'h20-addr, val, expected);
+           @(posedge i_gn4124.l2p_clk_p);
+        end
+
+      repeat(4) @(posedge clk_125m);
+
+      //  Check irq status
+      reg_check('h04, 'h04);
+      if (dma_irq != 1'b1)
+        $fatal(1, "dma irq should be 1");
+
+      // clear irq
+      acc.write('h04, 'h04);
+      reg_check('h04, 'h00);
+      if (dma_irq != 1'b0)
+        $fatal(1, "dma irq should be 0");
+
+      $write("PASS\n");

      #1us;