Commit 352c0db5 authored by Dimitris Lampridis's avatar Dimitris Lampridis

[hdl] sanitise folder structure

parent 4d45fbd7
if target=="xilinx":
modules = {
"local" : [
"hdl/gn4124core/rtl",
"hdl/rtl",
],
}
if action == "simulation":
modules['local'].append("hdl/gn4124core/sim/gn4124_bfm")
modules['local'].append("hdl/sim/gn4124_bfm")
......@@ -8,7 +8,7 @@ vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
include_dirs = [
"../gn4124_bfm",
......@@ -21,10 +21,9 @@ files = [
modules = {
"local" : [
"../gn4124_bfm",
"../../rtl",
"../../../",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"https://ohwr.org/project/general-cores.git",
],
}
files = ["dummy_ctrl_regs.vhd",
"dummy_stat_regs.vhd",
"wb_addr_decoder.vhd"]
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from dummy_ctrl_regs_wb_slave.wb
-- Created : Fri May 13 11:28:38 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dummy_ctrl_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_ctrl_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Ports for PASS_THROUGH field: 'IRQ' in reg: 'DUMMY_1'
dummy_reg_1_o : out std_logic_vector(31 downto 0);
dummy_reg_1_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_reg_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_reg_3_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for LED control' in reg: 'DUMMY_LED'
dummy_reg_led_o : out std_logic_vector(31 downto 0)
);
end dummy_ctrl_regs_wb_slave;
architecture syn of dummy_ctrl_regs_wb_slave is
signal dummy_reg_2_int : std_logic_vector(31 downto 0);
signal dummy_reg_3_int : std_logic_vector(31 downto 0);
signal dummy_reg_led_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dummy_reg_1_wr_o <= '0';
dummy_reg_2_int <= "00000000000000000000000000000000";
dummy_reg_3_int <= "00000000000000000000000000000000";
dummy_reg_led_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dummy_reg_1_wr_o <= '0';
ack_in_progress <= '0';
else
dummy_reg_1_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
dummy_reg_1_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
dummy_reg_2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_2_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
dummy_reg_3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_3_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
dummy_reg_led_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_led_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- IRQ
-- pass-through field: IRQ in register: DUMMY_1
dummy_reg_1_o <= wrdata_reg(31 downto 0);
-- Dummy register 2
dummy_reg_2_o <= dummy_reg_2_int;
-- Dummy register 3
dummy_reg_3_o <= dummy_reg_3_int;
-- Dummy register for LED control
dummy_reg_led_o <= dummy_reg_led_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy status registers
---------------------------------------------------------------------------------------
-- File : ../../GN4124_core/hdl/gn4124core/design/rtl/dummy_stat_regs.vhd
-- Author : auto-generated by wbgen2 from ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_stat_regs_wb_slave.wb
-- Created : Wed Nov 10 14:42:59 2010
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_stat_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_stat_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 1' in reg: 'DUMMY_1'
dummy_stat_reg_1_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_stat_reg_2_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_stat_reg_3_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for switch status' in reg: 'DUMMY_SWITCH'
dummy_stat_reg_switch_i : in std_logic_vector(31 downto 0)
);
end dummy_stat_regs_wb_slave;
architecture syn of dummy_stat_regs_wb_slave is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_3_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_switch_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Dummy register 1
-- Dummy register 2
-- Dummy register 3
-- Dummy register for switch status
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: wishbone address decoder
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 02-08-2011
--
-- version: 0.1
--
-- description: Provides a simple wishbone address decoder.
-- Splits the memory windows into equal parts.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes:
--------------------------------------------------------------------------------
-- TODO:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
entity wb_addr_decoder is
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end wb_addr_decoder;
architecture behaviour of wb_addr_decoder is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Wishbone
signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
signal s_wb_ack_muxed : std_logic;
signal wb_ack_t : std_logic;
signal s_wb_dat_i_muxed : std_logic_vector(31 downto 0);
signal s_wb_cyc_demuxed : std_logic_vector(g_WB_SLAVES_NB-1 downto 0);
signal wb_adr_t : std_logic_vector(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone master address decoding
------------------------------------------------------------------------------
-- Take the first N bits of the address to select the active wb peripheral
-- g_WINDOW_SIZE represents 32-bit word address window
s_wb_periph_addr <= wbm_adr_i(g_WINDOW_SIZE-1 downto g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB));
-----------------------------------------------------------------------------
-- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr);
-----------------------------------------------------------------------------
onehot_decode : process(s_wb_periph_addr)
variable v_onehot : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
variable v_index : integer range 0 to (2**s_wb_periph_addr'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in s_wb_periph_addr'range loop
if (s_wb_periph_addr(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
s_wb_periph_select <= v_onehot;
end process onehot_decode;
-- Register multiplexed ack and data + periph address
p_wb_in_regs : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_periph_addr <= (others => '0');
wbm_dat_o <= (others => '0');
wb_ack_t <= '0';
elsif rising_edge(clk_i) then
wb_periph_addr <= s_wb_periph_addr;
wbm_dat_o <= s_wb_dat_i_muxed;
wb_ack_t <= s_wb_ack_muxed;
end if;
end process p_wb_in_regs;
wbm_ack_o <= wb_ack_t;
-- Select ack line of the active peripheral
p_ack_mux : process (wb_ack_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_ack_muxed <= wb_ack_i(to_integer(unsigned(wb_periph_addr)));
else
s_wb_ack_muxed <= '0';
end if;
end process p_ack_mux;
-- Select stall line of the active peripheral
p_stall_mux : process (wb_stall_i, s_wb_periph_addr)
begin
if (to_integer(unsigned(s_wb_periph_addr)) < g_WB_SLAVES_NB) then
wbm_stall_o <= wb_stall_i(to_integer(unsigned(s_wb_periph_addr)));
else
wbm_stall_o <= '0';
end if;
end process p_stall_mux;
-- Select input data of the active peripheral
p_din_mux : process (wb_dat_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_dat_i_muxed <=
wb_dat_i(31+(32*to_integer(unsigned(wb_periph_addr))) downto 32*to_integer(unsigned(wb_periph_addr)));
else
s_wb_dat_i_muxed <= (others => 'X');
end if;
end process p_din_mux;
-- Assert the cyc line of the selected peripheral
gen_cyc_demux : for i in 0 to g_WB_SLAVES_NB-1 generate
s_wb_cyc_demuxed(i) <= wbm_cyc_i and s_wb_periph_select(i) and not(wb_ack_t);
end generate gen_cyc_demux;
-- Slaves wishbone bus outputs
wb_dat_o <= wbm_dat_i;
wb_stb_o <= wbm_stb_i;
wb_we_o <= wbm_we_i;
wb_sel_o <= wbm_sel_i;
wb_cyc_o <= s_wb_cyc_demuxed;
-- extend address bus to 32-bit
wb_adr_t <= wbm_adr_i(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
wb_adr_o(wb_adr_t'left downto 0) <= wb_adr_t;
wb_adr_o(31 downto wb_adr_t'left+1) <= (others => '0');
end behaviour;
peripheral {
name = "Dummy control registers";
description = "Wishbone slave for test of the CSR wishbone of the GN4124 core";
hdl_entity = "dummy_ctrl_regs_wb_slave";
prefix = "dummy_reg";
reg {
name = "DUMMY_1";
prefix = "1";
field {
name = "IRQ";
description = "Generates an IRQ";
type = PASS_THROUGH;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DUMMY_2";
prefix = "2";
field {
name = "Dummy register 2";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DUMMY_3";
prefix = "3";
field {
name = "Dummy register 3";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DUMMY_LED";
prefix = "led";
field {
name = "Dummy register for LED control";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
peripheral {
name = "Dummy status registers";
description = "Wishbone slave for test of the CSR wishbone of the GN4124 core";
hdl_entity = "dummy_stat_regs_wb_slave";
prefix = "dummy_stat_reg";
reg {
name = "DUMMY_1";
prefix = "1";
field {
name = "Dummy register 1";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DUMMY_2";
prefix = "2";
field {
name = "Dummy register 2";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DUMMY_3";
prefix = "3";
field {
name = "Dummy register 3";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DUMMY_SWITCH";
prefix = "switch";
field {
name = "Dummy register for switch status";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
work/
Makefile
modelsim.ini
transcript*
vsim.wlf
usc.lst
action = "simulation"
sim_tool = "modelsim"
sim_top = "TB_SPEC"
target = "xilinx"
vcom_opt = "-93"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
modules = {
"local" : [
"../top",
"../rtl",
"../../gn4124core/rtl",
"testbench",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
fetchto = "../../ip_cores"
//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: cont_block_dma.c
//**
//** Description: DMA scenario for a 2MB contiguous block of memory.
//**
//**
//***********************************************************************************************
//***********************************************************************************************
//===============================================================================================
// This provides the framework for creating tests for the testbench as described in
// GN412x Simulation Test Bench User Guide
//===============================================================================================
#include "lib/maketest.c"
//===============================================================================================
// This provides the framework for creating microcode for the 3 or 4DW list type described in
// the application note: "Implementing Multi-channel DMA with the GN412x IP"
//===============================================================================================
#include "lib/vdma_service.c"
//===============================================================================================
// lambo.h contains the address map for the Lambo project
//===============================================================================================
#include "lambo.h"
//===============================================================================================
// Define the Memory Map
//===============================================================================================
#define BAR0_BASE 0xFF00000010000000ll
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x87654321F0000000ll
#define BFM_BAR1_BASE 0xBB00000040000000ll
#define CHAN0_DESC_LIST_SIZE 3
#define L2P_CHAN0_SUB_DMA_LENGTH 0x1000
#define L2P_CHAN0_XFER_CTL 0x00010000
//===============================================================================================
// Define the SG List
//===============================================================================================
struct sg_entry_struct sg_list_chan0[] =
{
{ BFM_BAR0_BASE|0xFF1000C8, L2P_CHAN0_XFER_CTL | 0xF38, 1 },
{ BFM_BAR0_BASE|0xFF101000, L2P_CHAN0_XFER_CTL | (L2P_CHAN0_SUB_DMA_LENGTH & 0xFFF), 511 },
{ BFM_BAR0_BASE|0xFF300000, L2P_CHAN0_XFER_CTL | 0x0C8 | 0x80000000, 1 }, //Assert an interrupt
{ 0x0ll, 0, 0 }
};
//***********************************************************************************************
//**
//** vdma_main: This will insert the DMA microcode and data into the test script
//**
//** The last function call, vdma_process(), will cross reference all of the labels in the
//** source code so that you end up with the proper hexadecimal values that need to be written
//** to descriptor RAM.
//**
//***********************************************************************************************
void vdma_main()
{
vdma_org(0x0000); //This initializes the program address counter
data_address = 0x200; //This initializes the data space address counter
vdma_label("START");
vdma_nop(); //do nothing
//===============================================================================================
// START of the main program loop
//===============================================================================================
vdma_label("MAIN");
vdma_channel_service_4
(
"L2P_CHAN0", //label to be used for this specific channel
'l', //direction='l' for l2p or 'p' for p2l
0, //The event register bit to be used for interrupt generation
_EXT_COND_0, //External condition used for this channel
_EXT_COND_LO, //Set to either _EXT_COND_LO or _EXT_COND_HI
0, //set to non zero when the list will be updated dynamicaly
CHAN0_DESC_LIST_SIZE, //SYS_ADDR step size of list entries that have a repeat count
L2P_CHAN0_SUB_DMA_LENGTH, //Step size of list entries that have a repeat count
sg_list_chan0 //SG List itself
);
vdma_nop(); // This is not required (can be replaced with more channel servicing)
vdma_jmp(_ALWAYS, 0,"MAIN"); //loop forever
//===============================================================================================
// END of the main program loop
//===============================================================================================
//-----------------------------------------------------------------------------------------------
// Global Constants
//-----------------------------------------------------------------------------------------------
vdma_org(0x0100);
vdma_label("ZERO");
vdma_constant_n64(0); //The constant 0
vdma_label("MINUS1");
vdma_constant_n(0xFFFFFFFF); //The constant -1
vdma_label("THREE");
vdma_constant_n(3); //The constant 3
vdma_label("FOUR");
vdma_constant_n(4); //The constant 4
//===============================================================================================
// Must run vdma_process to resolve the cross-references and generate the microcode
//===============================================================================================
vdma_process(BAR0_BASE + 0x4000);
}
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
int offset=0, i;
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x20000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x10000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-------------------------------------------------------------------------------");
comment("DO some setup");
comment("-------------------------------------------------------------------------------");
comment("Lambo setup...");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(0x100);
wr(BAR0_BASE + DMA_SEQ_DPTR_REG, 0xF, 0x0);
wr(BAR0_BASE + DMA_SEQ_EVENT_EN_REG, 0xF, 0x3);
wr(BAR0_BASE + DMA_SEQ_EVENT_CLR_REG, 0xF, 0xFFFFFFFF);
wr(BAR0_BASE + APP_CFG, 0xF, 0x6);
wr(BAR0_BASE + APP_CFG, 0xF, 0x0);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x1F);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x7);
wr(BAR0_BASE + APP_GEN_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_ERR_COUNT, 0xF, 0x0);
wr(BAR0_BASE + DMA_PAYLOAD_SIZE, 0xF, 0x8020);
comment("\n-------------------------------------------------------------------------------");
comment("Setup the DMA microcode");
comment("-------------------------------------------------------------------------------");
vdma_main();
comment("\nStart VDMA");
wr(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x1);
comment("\n-------------------------------------------------------------------------------");
comment("Wait for an Interrupt for Channel 0");
comment("-------------------------------------------------------------------------------");
gpio_wait(8000, 0x0001, 0x0001);
comment("Clear the interrupt");
wr(BAR0_BASE + DMA_SEQ_EVENT_CLR_REG, 0xF, 0x00000001);
comment("\nRead VDMA idle status");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(5000);
wait(16);
//================================================================================================
//== END of user script
//================================================================================================
fclose(outfp);
exit(0);
}
#define DMA_STATUS_MASK 0x0000
#define DMA_CFG 0x0004
#define DMA_SEQ_EVENT_SET_REG 0x0008
#define DMA_SEQ_EVENT_CLR_REG 0x000C
#define DMA_SEQ_EVENT_REG 0x0010
#define DMA_SEQ_EVENT_EN_REG 0x0014
#define DMA_SEQ_ADDR_LOW_REG 0x0018
#define DMA_SEQ_ADDR_HI_REG 0x001C
#define DMA_SEQ_DPTR_REG 0x0020
#define DMA_SEQ_XFER_CTRL_REG 0x0024
#define DMA_SEQ_RA_REG 0x0028
#define DMA_SEQ_RB_REG 0x002C
#define DMA_SEQ_CSR_REG 0x0030
#define DMA_PAYLOAD_SIZE 0x0034
#define DMA_STATUS 0x0038
#define DMA_STATUS_RAW 0x003C
#define APP_STATUS_MASK 0x0050
#define APP_CFG 0x0054
#define APP_GEN_COUNT 0x0058
#define APP_RCV_COUNT 0x005C
#define APP_RCV_ERR_COUNT 0x0060
#define APP_STATUS 0x0064
#define APP_STATUS_RAW 0x0068
#define DMA_SEQ_DESC_RAM 0x4000
//---------------------------------------------------------------------------
/*
* Name: vdma_gen.c
*
* Description: Main Program for Generating VDMA Sequencer Code.
*
*/
#include "stdio.h"
#include "ctype.h"
#include "string.h"
#include "stdlib.h"
//#include "malloc.h"
#include "vdma_seqcode.h"
//#include "vdma_gen_struct.h"
#define VDMA_DRAM_SIZE 2048 // Size in DW of the descriptor RAM
#define MAX_LABELS 2048 // Maximum number of labels
#define MAX_COMMENT 200
#define MAX_LABEL_SIZE 32
struct
{
DWORD data;
char *label;
char comment[MAX_COMMENT+1];
} dram[VDMA_DRAM_SIZE+1];
struct
{
char *label; // label string
int address; // Address of the label
} vdma_labels[MAX_LABELS];
int label_compare(char *string1, char *string2)
{
if((string1 == NULL) || (string2 == NULL) || (*string1 == '\0') || (*string2 == '\0'))
return(0); /* no match */
else if(strlen(string1) != strlen(string2))
return(0); /* no match */
else
return(strcmp(string1, string2) == 0);
}
int program_address = 0;
int label_pointer = 0;
char last_label[100];
char out_filename[256];
FILE *outfp;
FILE *infp;
#include "model.c"
#include "vdma_seqcode_lib.c"
#define BAR0_ADDR_H ((DWORD)0xFF000000)
#define BAR0_ADDR_L ((DWORD)0x10000000)
//================================================================================================
//
// Do Some Initialization
//
//================================================================================================
maketest_init(argc,argv)
int argc;
char *argv[];
{
int i;
char *src, *dst;
// char filename[256];
src = argv[0];
dst = out_filename;
for(i=0; i<250; i++)
{
*dst = *src;
if(*src == '\0')
{
dst[0]='.';
dst[1]='h';
dst[2]='e';
dst[3]='x';
dst[4]='\0';
break;
}
if(*src == '.')
{
dst[1]='h';
dst[2]='e';
dst[3]='x';
dst[4]='\0';
break;
}
dst++;
src++;
}
/* Open the Hex Output File */
if((outfp = fopen(out_filename,"wb")) == NULL)
{
fprintf(stderr, "Couldn't open file %s for writing\n", out_filename);
exit(-2);
}
clearerr(outfp);
fprintf(stderr, "Output file %s is open...\n", out_filename);
/* initialize the label structure */
for(i = 0; i < MAX_LABELS; i++)
{
vdma_labels[i].label = NULL;
vdma_labels[i].address = -1;
}
/* initialize the descriptor RAM structure */
for(i = 0; i < VDMA_DRAM_SIZE; i++)
{
dram[i].label = NULL;
dram[i].data = 0;
dram[i].comment[0] = '\0';
}
program_address = 0;
label_pointer = 0;
last_label[0] = '\0';
fprintf(stderr, "Initialization complete\n");
comment("***********************************************************************************");
comment("*** Warning: this file is automatically generated. ***");
comment("***********************************************************************************");
comment("*** Do not edit this file directly as it is not the source! ***");
comment("***********************************************************************************");
}
vdma_process(U64 descriptor_base)
{
int i=0;
int lines=0;
int im;
int address;
fprintf(stderr, "Pass one complete:\n");
fprintf(stderr, " Processed %d labels\n", label_pointer);
fprintf(stderr, " Ended with program address=0x%04X\n", program_address);
//---------------------------------------------------------------------------------
// 2nd Pass: Now resolve label references
//---------------------------------------------------------------------------------
for(program_address = 0; program_address < VDMA_DRAM_SIZE; program_address++)
{
if((dram[program_address].label != NULL) && (dram[program_address].label[0] != '\0')) /* resolve the label */
{
//fprintf(stderr, "Resolving label %s at address=0x%04X\n", dram[program_address].label, program_address);
if(vdma_label_lookup(dram[program_address].label, &address))
{
dram[program_address].data |= address & 0xFFFF;
}
else
{
if((dram[program_address].label[0] == '0') && (tolower(dram[program_address].label[1]) == 'x')) // case of the label being a number
{
if(sscanf(&dram[program_address].label[2], "%x", &im) == 1)
dram[program_address].data |= im & 0xFFFF;
else
fprintf(stderr, "ERROR: could not resolve label %s. Appears to be a hex value?\n", dram[program_address].label);
}
else
fprintf(stderr, "ERROR: could not resolve label %s\n", dram[program_address].label);
}
i++;
}
//fprintf(stderr, "%d\n", program_address);
if(dram[program_address].label != NULL)
{
fprintf(outfp, "0x%04X\t0x%08lX\t%s\n", program_address, dram[program_address].data, dram[program_address].comment);
fprintf(stdout, "-- 0x%04X 0x%08lX %s\n", program_address, dram[program_address].data, dram[program_address].comment);
wr(descriptor_base + (program_address*4), 0xF, dram[program_address].data);
//fprintf(stdout, "wrb %08lX%08lX F %08lX\n", 0xFF000000, program_address, dram[program_address].data);
lines++;
}
}
fprintf(outfp, "// Label Listing:\n");
// Put the label table into the output file
for(i = 0; i < label_pointer; i++)
{
fprintf(outfp, "// 0x%04X : \"%s\"\n", vdma_labels[i].address, vdma_labels[i].label);
}
// label_pointer = 0;
fprintf(stderr, "Pass two complete:\n");
fprintf(stderr, " Substituted %d references in %d words of program and data space\n", i, lines);
fprintf(stderr, " Created output file \"%s\"\n", out_filename);
}
This diff is collapsed.
//---------------------------------------------------------------------------
/*
* Name: vdma_seqcode.h
*
* Description: FlexDMA sequencer instruction macros.
*
*/
#ifndef _VDMA_SEQCODE_H_
#define _VDMA_SEQCODE_H_
//Warning message during compilation to indicate macros are used
#pragma message("***** VDMA_CODE_GEN_MACRO is defined *****")
#ifndef DWORD
#define DWORD unsigned long
#endif
/*************************************************
VDMA sequencer code Definitions
*************************************************/
#define _IM (0)
#define _RA (2)
#define _RB (3)
//Condition code for JMP instruction
#define _RA_EQZ (0x8)
#define _RA_NEQZ (0)
#define _RB_EQZ (0x9)
#define _RB_NEQZ (1)
#define _ALWAYS (0xA)
#define _NEVER (0x2)
#define _C_HI (0xB)
#define _C_LO (0x3)
#define _PDM_CMD_QUEUE_FULL_HI (0xC)
#define _PDM_CMD_QUEUE_FULL_LO (0x4)
#define _LDM_CMD_QUEUE_FULL_HI (0xD)
#define _LDM_CMD_QUEUE_FULL_LO (0x5)
#define _EXT_COND_HI (0xF)
#define _EXT_COND_LO (0x7)
//External condition select code for JMP instruction
#define _PDM_IDLE (32)
#define _LDM_IDLE (33)
#define _EXT_COND_0 (34)
#define _EXT_COND_1 (35)
#define _EXT_COND_2 (36)
#define _EXT_COND_3 (37)
#define _EXT_COND_4 (38)
#define _EXT_COND_5 (39)
#define _EXT_COND_6 (40)
#define _EXT_COND_7 (41)
#define _EXT_COND_8 (42)
#define _EXT_COND_9 (43)
#define _EXT_COND_10 (44)
#define _EXT_COND_11 (45)
#define _EXT_COND_12 (46)
#define _EXT_COND_13 (47)
#define _EXT_COND_14 (48)
#define _EXT_COND_15 (49)
// VDMA instructions
#define VDMA_NOP() \
((DWORD)0x0)
#define VDMA_LOAD_SYS_ADDR(R, ADDR) \
((DWORD)0x40000000 | \
((DWORD)(R & 0x3) << 24) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_STORE_SYS_ADDR(R, ADDR) \
((DWORD)0x50000000 | \
((DWORD)(R & 0x3) << 24) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_ADD_SYS_ADDR(DATA) \
((DWORD)0x60000000 | \
((DWORD)(DATA & 0xFFFF)) \
)
#define VDMA_ADD_SYS_ADDR_I(ADDR) \
((DWORD)0xE0000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_LOAD_XFER_CTL(R, ADDR) \
((DWORD)0xF0000000 | \
((DWORD)(R & 0x3) << 24) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_LOAD_RA(ADDR) \
((DWORD)0x20000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_ADD_RA(ADDR) \
((DWORD)0x21000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_LOAD_RB(ADDR) \
((DWORD)0x24000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_ADD_RB(ADDR) \
((DWORD)0x25000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_STORE_RA(ADDR) \
((DWORD)0xA2000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_STORE_RB(ADDR) \
((DWORD)0xA3000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_JMP(C, EXT_COND, ADDR) \
((DWORD)0x10000000 | \
(DWORD)((C & 0xF) << 24) | \
(DWORD) ((EXT_COND & 0xFF) << 16) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_SIG_EVENT(S, A, EVENT_EN) \
((DWORD)0x80000000 | \
((DWORD)(S & 0x1) << 27) | \
((DWORD)(A & 0x1) << 26) | \
((DWORD)(EVENT_EN & 0xFFFF)) \
)
#define VDMA_WAIT_EVENT(EVENT_EN, EVENT_STATE) \
((DWORD)0x90000000 | \
((DWORD)((EVENT_EN & 0xFFF) << 12)) | \
((DWORD)(EVENT_STATE & 0xFFF)) \
)
#endif
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This diff is collapsed.
//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: simple.c
//**
//** Description: This is an example test source code used to drive the Lambo TestBench.
//**
//***********************************************************************************************
//***********************************************************************************************
#include "lib/maketest.c"
#define BAR0_BASE 0xFF00000010000000ll
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x8765432120000000ll
#define BFM_BAR1_BASE 0xBB00000040000000ll
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x08000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x20000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-----------------------------------------------------------------------------");
comment("Access the descriptor memory in the Lambo design");
comment("-----------------------------------------------------------------------------");
comment("the following three writes will go out in a single packet");
wrb(BAR0_BASE+0x4000, 0xF, 0x87654321);
wrb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE);
wr( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF);
comment("\nNow read back what was just written");
comment("the following three reads will go out as a single request");
rdb(BAR0_BASE+0x4000, 0xF, 0x87654321, 0xFFFFFFFF);
rdb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE, 0xFFFFFFFF);
rd( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF, 0xFFFFFFFF);
comment("\n");
flush(256);
comment("\n");
wait(16);
comment("\n");
sync();
//================================================================================================
//== END of user script
//================================================================================================
exit(0);
}
This diff is collapsed.
//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: simple.c
//**
//** Description: This is an example test source code used to drive the Lambo TestBench.
//**
//***********************************************************************************************
//***********************************************************************************************
#include "lib/maketest.c"
#define BAR0_BASE 0xFF00000010000000ll
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x8765432120000000ll
#define BFM_BAR1_BASE 0xBB00000040000000ll
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x08000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x20000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-----------------------------------------------------------------------------");
comment("Access the descriptor memory in the Lambo design");
comment("-----------------------------------------------------------------------------");
comment("the following three writes will go out in a single packet");
wrb(BAR0_BASE+0x4000, 0xF, 0x87654321);
wrb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE);
wr( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF);
comment("\nNow read back what was just written");
comment("the following three reads will go out as a single request");
rdb(BAR0_BASE+0x4000, 0xF, 0x87654321, 0xFFFFFFFF);
rdb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE, 0xFFFFFFFF);
rd( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF, 0xFFFFFFFF);
comment("\n");
flush(256);
comment("\n");
wait(16);
comment("\n");
sync();
//================================================================================================
//== END of user script
//================================================================================================
exit(0);
}
-------------------------------------------------------------------------------
-- Generated from: simple.c - do not edit the vec file directly as it is not the source!
-- Short example of using the lambo TestBench
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model %d0
-- Initialize the BFM to its default state
init
-- Drive reset to the FPGA
reset %d16
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 FF00000010000000 08000000 0 7 0
bar 1 FF000000A0000000 10000000 1 5 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 8765432120000000 20000000
bfm_bar 1 BB00000040000000 20000000
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d64
-------------------------------------------------------------------------------
-- Access the descriptor memory in the Lambo design
-------------------------------------------------------------------------------
-- the following three writes will go out in a single packet
wrb FF00000010004000 F 87654321
wrb FF00000010004004 F FEEDFACE
wr FF00000010004008 F DEADBEEF
-- Now read back what was just written
-- the following three reads will go out as a single request
rdb FF00000010004000 F 87654321 FFFFFFFF
rdb FF00000010004004 F FEEDFACE FFFFFFFF
rd FF00000010004008 F DEADBEEF FFFFFFFF
flush %d256
wait %d16
sync
//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: simple_dma.c
//**
//** Description: This is an example test source code used to drive the Lambo TestBench.
//**
//**
//***********************************************************************************************
//***********************************************************************************************
#include "lib/maketest.c" //This inserts the Test_Builder C framework
#include "lambo.h" //This is for the project specific registers
//===============================================================================================
// Define the Memory Map for the Simulation
//===============================================================================================
#define BAR0_BASE 0xFF00000010000000ll //rd/wr here generate LB cycles
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x8765432120000000ll //rd/wr here accesses internal BFM memory
#define BFM_BAR1_BASE 0xBB00000040000000ll
#define VDMA_DRAM_BASE (BAR0_BASE + 0x4000ll) //This is where the microcode will be written
//***********************************************************************************************
//**
//** VDMA Sequencer Microcode:
//**
//** The following microcode will get compiled and converted into a series of write cycles
//** so that the BFM will write the microcode into descriptor memory. The last function call
//** vdma_process() will cross reference all of the labels in the source code so that you
//** end up with the proper hexadecimal values that need to be written to descriptor RAM.
//**
//***********************************************************************************************
void vdma_main()
{
//===============================================================================================
// START of the main program loop
//===============================================================================================
// Example source code to be compiled into VDMA binarys or test bench script
vdma_org(0x0000);
vdma_label("MAIN");
vdma_nop();
vdma_label("DO_L2P0");
vdma_load_sys_addr(_IM,"L2P0_SYS_ADDR"); //Load system address from SG entry
vdma_load_xfer_ctl(_IM,"L2P0_XFER_CTL"); //Start DMA0
vdma_label("DO_L2P1");
vdma_load_sys_addr(_IM,"L2P1_SYS_ADDR"); //Load system address from SG entry
vdma_load_xfer_ctl(_IM,"L2P1_XFER_CTL"); //Start DMA1
vdma_label("WAIT4IDLE");
vdma_jmp(_EXT_COND_LO,_LDM_IDLE,"WAIT4IDLE"); //Loop until DMA idle
vdma_sig_event(0, 1, 0x0001);
vdma_label("FOREVER");
vdma_nop();
vdma_jmp(_ALWAYS, 0,"FOREVER"); //Loop forever
//===============================================================================================
// END of the main program loop
//===============================================================================================
//
//-----------------------------------------------------------------------------------------------
// Constants
//-----------------------------------------------------------------------------------------------
vdma_org(0x0100);
vdma_label("L2P0_SYS_ADDR");
vdma_constant_n64(BFM_BAR0_BASE+0x200); //L2P0 system address low/hi
vdma_label("L2P0_XFER_CTL");
vdma_constant_n(0x00010080); //L2P0 transfer control: 128B, STREAM_ID=1
vdma_label("L2P1_SYS_ADDR");
vdma_constant_n64(BFM_BAR1_BASE+0x200); //L2P1 system address low/hi
vdma_label("L2P1_XFER_CTL");
vdma_constant_n(0x00040080); //L2P1 transfer control: 128B, STREAM_ID=4
//===============================================================================================
// Must run vdma_process to resolve the cross-references and generate the memory writes
//===============================================================================================
vdma_process(VDMA_DRAM_BASE); // This actually printfs the data to the file
}
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x08000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x20000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-------------------------------------------------------------------------------");
comment("DO some setup");
comment("-------------------------------------------------------------------------------");
comment("Lambo setup...");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(0x100);
wr(BAR0_BASE + DMA_SEQ_DPTR_REG, 0xF, 0x0);
wr(BAR0_BASE + DMA_SEQ_EVENT_EN_REG, 0xF, 0x1);
wr(BAR0_BASE + DMA_SEQ_EVENT_CLR_REG, 0xF, 0xFFFFFFFF);
wr(BAR0_BASE + APP_CFG, 0xF, 0x6);
wr(BAR0_BASE + APP_CFG, 0xF, 0x0);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x1F);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x7);
wr(BAR0_BASE + APP_GEN_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_ERR_COUNT, 0xF, 0x0);
wr(BAR0_BASE + DMA_PAYLOAD_SIZE, 0xF, 0x8020);
comment("\n-------------------------------------------------------------------------------");
comment("Setup the DMA microcode");
comment("-------------------------------------------------------------------------------");
vdma_main();
comment("\nStart VDMA");
wr(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x1);
gpio_wait(300, 0x0001, 0x0001);
comment("\nRead VDMA idle status");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(256);
wait(16);
//================================================================================================
//== END of user script
//================================================================================================
fclose(outfp);
exit(0);
}
0x0000 0x00000000 MAIN: vdma_nop()
0x0001 0x40000100 DO_L2P0: vdma_load_sys_addr(r=_IM, "L2P0_SYS_ADDR")
0x0002 0xF0000102 vdma_load_xfer_ctl(_IM, "L2P0_XFER_CTL")
0x0003 0x40000103 DO_L2P1: vdma_load_sys_addr(r=_IM, "L2P1_SYS_ADDR")
0x0004 0xF0000105 vdma_load_xfer_ctl(_IM, "L2P1_XFER_CTL")
0x0005 0x17210005 WAIT4IDLE: vdma_jmp(c=_EXT_COND_LO, ext_cond=_LDM_IDLE, "WAIT4IDLE")
0x0006 0x84000001 vdma_sig_event(s=0, a=1, event_en=0x0001)
0x0007 0x00000000 FOREVER: vdma_nop()
0x0008 0x1A000007 vdma_jmp(c=_ALWAYS, ext_cond=NA, "FOREVER")
0x0100 0x20000200 L2P0_SYS_ADDR: vdma_constant_n64(0x8765432120000200)
0x0101 0x87654321 // vdma_constant_n64 - upper data
0x0102 0x00010080 L2P0_XFER_CTL: vdma_constant_n(0x00010080)
0x0103 0x40000200 L2P1_SYS_ADDR: vdma_constant_n64(0xBB00000040000200)
0x0104 0xBB000000 // vdma_constant_n64 - upper data
0x0105 0x00040080 L2P1_XFER_CTL: vdma_constant_n(0x00040080)
// Label Listing:
// 0x0000 : "MAIN"
// 0x0001 : "DO_L2P0"
// 0x0003 : "DO_L2P1"
// 0x0005 : "WAIT4IDLE"
// 0x0007 : "FOREVER"
// 0x0100 : "L2P0_SYS_ADDR"
// 0x0102 : "L2P0_XFER_CTL"
// 0x0103 : "L2P1_SYS_ADDR"
// 0x0105 : "L2P1_XFER_CTL"
TESTBENCH = testbench
DDRMODEL = sim_models/2048Mb_ddr3
SPEC = ../rtl
GNCORE = ../../../../GN4124_core/hdl/gn4124core/rtl
GNCORE_IP = ../../../../GN4124_core/hdl/spec/ip_cores
DDRCORE = ../../../../ddr3_ctrl_core/hdl/rtl
DDRCORE_IP = ../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl
# These are the technology specific files
#GLBL = unisims
#FPGA = unisims
VHDL_LIB = testbench
MK = mk
# Change VCOM and VLOG for use with other simulation tools
VCOM = vcom
VLOG = vlog
TOUCH = echo "" > $@
spec : $(MK)/tb_spec.mk
bfm : $(MK)/tb_gn412x.mk
clean :
rm -f $(MK)/*.mk
vdel -lib work -all
vlib work
##################################################################################################
# SPEC Test Bench Project
##################################################################################################
$(MK)/tb_spec.mk : $(TESTBENCH)/tb_spec.vhd $(MK)/spec_ddr_test.mk $(MK)/gn412x_bfm.mk $(MK)/cmd_router.mk \
$(MK)/ddr3.mk
$(VCOM) $(TESTBENCH)/tb_spec.vhd
$(TOUCH)
##################################################################################################
# SPEC Project
##################################################################################################
$(MK)/spec_ddr_test.mk : $(SPEC)/spec_ddr_test.vhd $(MK)/gn4124_core.mk \
$(MK)/gpio_regs.mk $(MK)/ddr3_ctrl.mk
$(VCOM) $(SPEC)/spec_ddr_test.vhd
$(TOUCH)
$(MK)/gpio_regs.mk : $(SPEC)/gpio_regs.vhd
$(VCOM) $(SPEC)/gpio_regs.vhd
$(TOUCH)
# GN4124 core
$(MK)/gn4124_core.mk : $(GNCORE)/spartan6/gn4124_core.vhd $(MK)/gn4124_core_pkg.mk $(MK)/p2l_des.mk \
$(MK)/p2l_decode32.mk $(MK)/wbmaster32.mk $(MK)/l2p_arbiter.mk $(MK)/l2p_ser.mk \
$(MK)/dma_controller.mk $(MK)/l2p_dma_master.mk $(MK)/p2l_dma_master.mk \
$(MK)/serdes_1_to_n_clk_pll_s2_diff.mk
$(VCOM) $(GNCORE)/spartan6/gn4124_core.vhd
$(TOUCH)
$(MK)/gn4124_core_pkg.mk : $(GNCORE)/spartan6/gn4124_core_pkg.vhd
$(VCOM) $(GNCORE)/spartan6/gn4124_core_pkg.vhd
$(TOUCH)
$(MK)/p2l_des.mk : $(GNCORE)/spartan6/p2l_des.vhd $(MK)/serdes_1_to_n_data_s2_se.mk
$(VCOM) $(GNCORE)/spartan6/p2l_des.vhd
$(TOUCH)
$(MK)/p2l_decode32.mk : $(GNCORE)/p2l_decode32.vhd
$(VCOM) $(GNCORE)/p2l_decode32.vhd
$(TOUCH)
$(MK)/wbmaster32.mk : $(GNCORE)/wbmaster32.vhd $(MK)/fifo_32x512.mk $(MK)/fifo_64x512.mk
$(VCOM) $(GNCORE)/wbmaster32.vhd
$(TOUCH)
$(MK)/l2p_arbiter.mk : $(GNCORE)/l2p_arbiter.vhd
$(VCOM) $(GNCORE)/l2p_arbiter.vhd
$(TOUCH)
$(MK)/dma_controller.mk : $(GNCORE)/dma_controller.vhd $(MK)/dma_controller_wb_slave.mk
$(VCOM) $(GNCORE)/dma_controller.vhd
$(TOUCH)
$(MK)/l2p_dma_master.mk : $(GNCORE)/l2p_dma_master.vhd $(MK)/fifo_32x512.mk
$(VCOM) $(GNCORE)/l2p_dma_master.vhd
$(TOUCH)
$(MK)/p2l_dma_master.mk : $(GNCORE)/p2l_dma_master.vhd $(MK)/fifo_64x512.mk
$(VCOM) $(GNCORE)/p2l_dma_master.vhd
$(TOUCH)
$(MK)/dma_controller_wb_slave.mk : $(GNCORE)/dma_controller_wb_slave.vhd
$(VCOM) $(GNCORE)/dma_controller_wb_slave.vhd
$(TOUCH)
$(MK)/l2p_ser.mk : $(GNCORE)/spartan6/l2p_ser.vhd $(MK)/serdes_n_to_1_s2_se.mk \
$(MK)/serdes_n_to_1_s2_diff.mk
$(VCOM) $(GNCORE)/spartan6/l2p_ser.vhd
$(TOUCH)
$(MK)/serdes_1_to_n_clk_pll_s2_diff.mk : $(GNCORE)/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
$(TOUCH)
$(MK)/serdes_1_to_n_data_s2_se.mk : $(GNCORE)/spartan6/serdes_1_to_n_data_s2_se.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_1_to_n_data_s2_se.vhd
$(TOUCH)
$(MK)/serdes_n_to_1_s2_se.mk : $(GNCORE)/spartan6/serdes_n_to_1_s2_se.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_n_to_1_s2_se.vhd
$(TOUCH)
$(MK)/serdes_n_to_1_s2_diff.mk : $(GNCORE)/spartan6/serdes_n_to_1_s2_diff.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_n_to_1_s2_diff.vhd
$(TOUCH)
$(MK)/fifo_32x512.mk : $(GNCORE_IP)/fifo_32x512.vhd
$(VCOM) $(GNCORE_IP)/fifo_32x512.vhd
$(TOUCH)
$(MK)/fifo_64x512.mk : $(GNCORE_IP)/fifo_64x512.vhd
$(VCOM) $(GNCORE_IP)/fifo_64x512.vhd
$(TOUCH)
# DDR3 core
$(MK)/ddr3_ctrl.mk : $(DDRCORE)/ddr3_ctrl.vhd $(MK)/ddr3_ctrl_wb.mk $(MK)/ddr3_ctrl_wrapper.mk
$(VCOM) $(DDRCORE)/ddr3_ctrl.vhd
$(TOUCH)
$(MK)/ddr3_ctrl_wb.mk : $(DDRCORE)/ddr3_ctrl_wb.vhd
$(VCOM) $(DDRCORE)/ddr3_ctrl_wb.vhd
$(TOUCH)
$(MK)/ddr3_ctrl_wrapper.mk : $(DDRCORE)/../spec/rtl/ddr3_ctrl_wrapper.vhd $(MK)/ddr_ctrl_bank3.mk
$(VCOM) $(DDRCORE)/../spec/rtl/ddr3_ctrl_wrapper.vhd
$(TOUCH)
$(MK)/ddr_ctrl_bank3.mk : $(DDRCORE_IP)/ddr_ctrl_bank3.vhd $(MK)/memc3_infrastructure.mk $(MK)/memc3_wrapper.mk
$(VCOM) $(DDRCORE_IP)/ddr_ctrl_bank3.vhd
$(TOUCH)
$(MK)/memc3_infrastructure.mk : $(DDRCORE_IP)/memc3_infrastructure.vhd
$(VCOM) $(DDRCORE_IP)/memc3_infrastructure.vhd
$(TOUCH)
$(MK)/memc3_wrapper.mk : $(DDRCORE_IP)/memc3_wrapper.vhd $(MK)/mcb_raw_wrapper.mk
$(VCOM) $(DDRCORE_IP)/memc3_wrapper.vhd
$(TOUCH)
$(MK)/mcb_raw_wrapper.mk : $(DDRCORE_IP)/mcb_raw_wrapper.vhd $(MK)/mcb_soft_calibration_top.mk
$(VCOM) $(DDRCORE_IP)/mcb_raw_wrapper.vhd
$(TOUCH)
$(MK)/mcb_soft_calibration_top.mk : $(DDRCORE_IP)/mcb_soft_calibration_top.vhd $(MK)/mcb_soft_calibration.mk
$(VCOM) $(DDRCORE_IP)/mcb_soft_calibration_top.vhd
$(TOUCH)
$(MK)/mcb_soft_calibration.mk : $(DDRCORE_IP)/mcb_soft_calibration.vhd $(MK)/iodrp_controller.mk \
$(MK)/iodrp_mcb_controller.mk
$(VCOM) $(DDRCORE_IP)/mcb_soft_calibration.vhd
$(TOUCH)
$(MK)/iodrp_controller.mk : $(DDRCORE_IP)/iodrp_controller.vhd
$(VCOM) $(DDRCORE_IP)/iodrp_controller.vhd
$(TOUCH)
$(MK)/iodrp_mcb_controller.mk : $(DDRCORE_IP)/iodrp_mcb_controller.vhd
$(VCOM) $(DDRCORE_IP)/iodrp_mcb_controller.vhd
$(TOUCH)
##################################################################################################
# Test Bench Project
##################################################################################################
$(MK)/tb_gn412x.mk : $(TESTBENCH)/tb_gn412x.vhd $(MK)/gn412x_bfm.mk $(MK)/cmd_router.mk
$(VCOM) $(TESTBENCH)/tb_gn412x.vhd
$(TOUCH)
$(MK)/gn412x_bfm.mk : $(TESTBENCH)/gn412x_bfm.vhd $(MK)/textutil.mk $(MK)/mem_model.mk
$(VCOM) $(TESTBENCH)/gn412x_bfm.vhd
$(TOUCH)
$(MK)/mem_model.mk : $(VHDL_LIB)/mem_model.vhd
$(VCOM) -87 $(VHDL_LIB)/mem_model.vhd
$(TOUCH)
$(MK)/textutil.mk : $(VHDL_LIB)/textutil.vhd $(MK)/util.mk
$(VCOM) $(VHDL_LIB)/textutil.vhd
$(TOUCH)
$(MK)/util.mk : $(VHDL_LIB)/util.vhd
$(VCOM) $(VHDL_LIB)/util.vhd
$(TOUCH)
$(MK)/cmd_router.mk : $(TESTBENCH)/cmd_router.vhd $(MK)/cmd_router1.mk $(MK)/textutil.mk
$(VCOM) $(TESTBENCH)/cmd_router.vhd
$(TOUCH)
$(MK)/cmd_router1.mk : $(TESTBENCH)/cmd_router1.vhd $(MK)/textutil.mk
$(VCOM) $(TESTBENCH)/cmd_router1.vhd
$(TOUCH)
# DDR3 model
$(MK)/ddr3.mk : $(DDRMODEL)/ddr3.v
$(VLOG) +incdir+$(DDRMODEL) +define+sg15E +define+x16 $(DDRMODEL)/ddr3.v
$(TOUCH)
-- ***********************************************************************************
-- *** Warning: this file is automatically generated. ***
-- ***********************************************************************************
-- *** Do not edit this file directly as it is not the source! ***
-- ***********************************************************************************
-------------------------------------------------------------------------------
-- Generated from: simple.c - do not edit the vec file directly as it is not the source!
-- Short example of using the lambo TestBench
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model %d0
-- Initialize the BFM to its default state
init
-- Drive reset to the FPGA
reset %d16
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 FF00000000000000 08000000 0 7 0
--bar 1 FF000000A0000000 10000000 1 5 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- bfm_bar 0 BB00000040000000 20000000
-- bfm_bar 1 00000000123456f8 20000000
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d64
-------------------------------------------------------------------------------
-- Access the descriptor memory in the Lambo design
-------------------------------------------------------------------------------
-- the following three writes will go out in a single packet
wr 0000000040000000 F C0FFEE82
wr 0000000040000004 F 00000001
wr 0000000040000008 F 00000002
wr 000000004000000C F 00000003
wr 0000000040000010 F 00000004
wr 0000000040000014 F 00000005
wr 0000000040000018 F 00000006
wr 000000004000001C F 00000007
wr 0000000040000020 F 00000008
wr 0000000040000024 F 00000009
wr 0000000040000028 F 0000000A
wr 000000004000002C F 0000000B
wr 0000000040000030 F 0000000C
wr 0000000040000034 F 0000000D
wr 0000000040000038 F 0000000E
wr 000000004000003C F 0000000F
wr 0000000040000040 F 00000010
wr 0000000040000044 F 00000011
wr 0000000040000048 F 00000012
wr 000000004000004C F 00000013
wr 0000000040000050 F 00000014
wr 0000000040000054 F 00000015
wr 0000000040000058 F 00000016
wr 000000004000005C F 00000017
wr 0000000040000060 F 00000018
wr 0000000040000064 F 00000019
wr 0000000040000068 F 0000001A
wr 000000004000006C F 0000001B
wr 0000000040000070 F 0000001C
wr 0000000040000074 F 0000001D
wr 0000000040000078 F 0000001E
wr 000000004000007C F 0000001F
wr 0000000040000080 F 00000020
wr 0000000040000084 F 00000021
wr 0000000040000088 F 00000022
wr 000000004000008C F 00000023
wr 0000000040000090 F 00000024
wr 0000000040000094 F 00000025
wr 0000000040000098 F 00000026
wr 000000004000009C F 00000027
wr 00000000400000A0 F 00000028
wr 00000000400000A4 F 00000029
wr 00000000400000A8 F 0000002A
wr 00000000400000AC F 0000002B
wr 00000000400000B0 F 0000002C
wr 00000000400000B4 F 0000002D
wr 00000000400000B8 F 0000002E
wr 00000000400000BC F 0000002F
wr 00000000400000C0 F 00000030
wr 0000000040000F00 F 00000F00
wr 0000000040000F04 F 00000F01
wr 0000000040000F08 F 00000F02
wr 0000000040000F0C F 00000F03
wr 0000000040000F10 F 00000F04
wr 0000000040000F14 F 00000F05
wr 0000000040000F18 F 00000F06
wr 0000000040000F1C F 00000F07
wr 0000000040000F20 F 00000F08
wr 0000000040000F24 F 00000F09
wr 0000000040000F28 F 00000F0A
wr 0000000040000F2C F 00000F0B
wr 0000000040000F30 F 00000F0C
wr 0000000040000F34 F 00000F0D
wr 0000000040000F38 F 00000F0E
wr 0000000040000F3C F 00000F0F
wr 0000000040000F40 F 00000F10
wr 0000000040000F44 F 00000F11
wr 0000000040000F48 F 00000F12
wr 0000000040000F4C F 00000F13
wr 0000000040000F50 F 00000F14
wr 0000000040000F54 F 00000F15
wr 0000000040000F58 F 00000F16
wr 0000000040000F5C F 00000F17
wr 0000000040000F60 F 00000F18
wr 0000000040000F64 F 00000F19
wr 0000000040000F68 F 00000F1A
wr 0000000040000F6C F 00000F1B
wr 0000000040000F70 F 00000F1C
wr 0000000040000F74 F 00000F1D
wr 0000000040000F78 F 00000F1E
wr 0000000040000F7C F 00000F1F
wr 0000000040000F80 F 00000F20
wr 0000000040000F84 F 00000F21
wr 0000000040000F88 F 00000F22
wr 0000000040000F8C F 00000F23
wr 0000000040000F90 F 00000F24
wr 0000000040000F94 F 00000F25
wr 0000000040000F98 F 00000F26
wr 0000000040000F9C F 00000F27
wr 0000000040000FA0 F 00000F28
wr 0000000040000FA4 F 00000F29
wr 0000000040000FA8 F 00000F2A
wr 0000000040000FAC F 00000F2B
wr 0000000040000FB0 F 00000F2C
wr 0000000040000FB4 F 00000F2D
wr 0000000040000FB8 F 00000F2E
wr 0000000040000FBC F 00000F2F
-- CSR wishbone test
rd FF00000000040000 F DEAD0000 FFFF0000
wr FF0000000008000C F 00000003
rd FF0000000008000C F 00000003 FFFFFFFF
wait %d640
-- DDR access trough CSR wishbone
--wr FF000000000C0004 F DEADC0DE
--wait %d300
--rd FF000000000C0004 F DEADC0DE FFFFFFFF
wait %d300
-- DDR access trough DMA wishbone
wr 0000000020000000 F 00000000
wr 0000000020000004 F 40000000
wr 0000000020000008 F 00000000
-- DMA length
wr 000000002000000C F 00000004
wr 0000000020000010 F 00000000
wr 0000000020000014 F 00000000
wr 0000000020000018 F 00000000
-- wrb FF00000010004004 F 00000000
wr FF00000000000008 F 00000000
wr FF0000000000000C F 40000000
wr FF00000000000010 F 00000000
-- DMA length
wr FF00000000000014 F 00000004
wr FF00000000000018 F 20000000
wr FF0000000000001C F 00000000
wr FF00000000000020 F 00000003
wr FF00000000000000 F 00000001
-- Now read back what was just written
-- the following three reads will go out as a single request
--rdb FF00000010004004 F FEEDFACE FFFFFFFF
--rdb FF00000010004008 F DBDBDBDB FFFFFFFF
--rd FF00000010004008 F DEADBEEF FFFFFFFF
--wrb FF0000001000401C F 00000000
--wrb FF00000010004024 F 00000000
--wr FF00000010004000 F 00000001
--rdb FF00000010004000 F 00000002 FFFFFFFF
--rdb FF00000010004004 F 00000000 FFFFFFFF
--rdb FF00000010004008 F 5A5A5A5A FFFFFFFF
--rdb FF0000001000400C F 12345678 FFFFFFFF
--rdb FF00000010004010 F 00000000 FFFFFFFF
--rdb FF00000010004014 F 00000010 FFFFFFFF
--rdb FF00000010004018 F 00000000 FFFFFFFF
--rdb FF0000001000401C F 00000000 FFFFFFFF
--rd FF00000010004020 F 00000000 FFFFFFFF
wait %d160
--wr FF00000010004000 F 00000001
--rd FF0000001000400C F DEADBEEF FFFFFFFF
--rd FF00000010004008 F ABABABAB FFFFFFFF
wait %d
flush %d256
wait %d16
sync
m255
K3
13
cModel Technology
Z0 d/home/mcattin/projects/GN4124_core/hdl_trunk/spec/sim
Exilinx_dummy_sim
w1311674401
Z1 d/home/mcattin/projects/GN4124_core/hdl_trunk/spec/sim
8../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
F../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
l0
L1
VKd8^[`j@TZDeV[[hfDI:J0
!s100 nF<;LZ6J0iDiIE_]ATjaA3
Z2 OE;C;6.6e_1;45
32
o-quiet -work fifo_generator_v6_1
Z3 tExplicit 1
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