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Gennum GN4124 core
Commits
578018b4
Commit
578018b4
authored
Aug 23, 2019
by
Tristan Gingold
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dma_controller: add register to read the current values.
parent
90539571
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3 changed files
with
78 additions
and
2 deletions
+78
-2
dma_controller.vhd
hdl/rtl/dma_controller.vhd
+5
-1
dma_controller_regs.cheby
hdl/rtl/dma_controller_regs.cheby
+20
-0
dma_controller_regs.vhd
hdl/rtl/dma_controller_regs.vhd
+53
-1
No files found.
hdl/rtl/dma_controller.vhd
View file @
578018b4
...
...
@@ -177,7 +177,11 @@ begin
nextl_o
=>
dma_nextl
,
nexth_o
=>
dma_nexth
,
attrib_chain_o
=>
dma_attrib_chain
,
attrib_dir_o
=>
dma_attrib_dir
);
attrib_dir_o
=>
dma_attrib_dir
,
cur_cstart_i
=>
dma_cstart_reg
,
cur_hstartl_i
=>
dma_hstartl_reg
,
cur_hstarth_i
=>
dma_hstarth_reg
,
cur_len_i
=>
dma_len_reg
);
-- Synchronizers for control.
inst_sync_ctrl
:
entity
work
.
gc_sync_word_wr
...
...
hdl/rtl/dma_controller_regs.cheby
View file @
578018b4
...
...
@@ -148,3 +148,23 @@ memory-map:
name: dir
comment: "Transfer direction (0: to host, 1: to carrier)"
range: 0
- reg:
name: cur_cstart
width: 32
access: ro
description: Current carrier start address
- reg:
name: cur_hstartl
width: 32
access: ro
description: Current DMA start address (low) in the host
- reg:
name: cur_hstarth
width: 32
access: ro
description: Current DMA start address (high) in the host
- reg:
name: cur_len
width: 32
access: ro
description: Current DMA read length in bytes
hdl/rtl/dma_controller_regs.vhd
View file @
578018b4
...
...
@@ -68,7 +68,19 @@ entity dma_controller_regs is
attrib_chain_o
:
out
std_logic
;
-- Transfer direction (0: to host, 1: to carrier)
attrib_dir_o
:
out
std_logic
attrib_dir_o
:
out
std_logic
;
-- Current carrier start address
cur_cstart_i
:
in
std_logic_vector
(
31
downto
0
);
-- Current DMA start address (low) in the host
cur_hstartl_i
:
in
std_logic_vector
(
31
downto
0
);
-- Current DMA start address (high) in the host
cur_hstarth_i
:
in
std_logic_vector
(
31
downto
0
);
-- Current DMA read length in bytes
cur_len_i
:
in
std_logic_vector
(
31
downto
0
)
);
end
dma_controller_regs
;
...
...
@@ -217,6 +229,14 @@ begin
attrib_dir_reg
<=
wb_dat_i
(
0
);
end
if
;
wr_ack_int
<=
wr_int
;
when
"1001"
=>
-- Register cur_cstart
when
"1010"
=>
-- Register cur_hstartl
when
"1011"
=>
-- Register cur_hstarth
when
"1100"
=>
-- Register cur_len
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
...
...
@@ -275,6 +295,22 @@ begin
reg_rdat_int
(
1
)
<=
attrib_chain_reg
;
reg_rdat_int
(
0
)
<=
attrib_dir_reg
;
rd_ack1_int
<=
rd_int
;
when
"1001"
=>
-- cur_cstart
reg_rdat_int
<=
cur_cstart_i
;
rd_ack1_int
<=
rd_int
;
when
"1010"
=>
-- cur_hstartl
reg_rdat_int
<=
cur_hstartl_i
;
rd_ack1_int
<=
rd_int
;
when
"1011"
=>
-- cur_hstarth
reg_rdat_int
<=
cur_hstarth_i
;
rd_ack1_int
<=
rd_int
;
when
"1100"
=>
-- cur_len
reg_rdat_int
<=
cur_len_i
;
rd_ack1_int
<=
rd_int
;
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
...
...
@@ -324,6 +360,22 @@ begin
-- attrib
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1001"
=>
-- cur_cstart
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1010"
=>
-- cur_hstartl
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1011"
=>
-- cur_hstarth
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1100"
=>
-- cur_len
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
...
...
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