[hdl] Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master.

Note: P2L DMA already supported this for DMA writes.

[hdl] Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master.
Note: P2L DMA already supported this for DMA writes.
b0c817cc · Dimitris Lampridis · 91d5efac · b0c817cc · b0c817cc
Commit b0c817cc authored Aug 15, 2019 by Dimitris Lampridis
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l2p_dma_master.vhd hdl/rtl/l2p_dma_master.vhd +7 -7

main.sv hdl/sim/example_tb/main.sv +4 -5

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--- a/hdl/rtl/l2p_dma_master.vhd
+++ b/hdl/rtl/l2p_dma_master.vhd
@@ -122,7 +122,7 @@ architecture behavioral of l2p_dma_master is

    -- L2P packets
    signal s_l2p_header    : std_logic_vector(31 downto 0);
-    signal l2p_len_cnt     : unsigned(12 downto 0)         := (others => '0');
+    signal l2p_len_cnt     : unsigned(29 downto 0)         := (others => '0');
    signal l2p_address_h   : std_logic_vector(31 downto 0) := (others => '0');
    signal l2p_address_l   : std_logic_vector(31 downto 0) := (others => '0');
    signal l2p_data_cnt    : unsigned(12 downto 0)         := (others => '0');
@@ -136,7 +136,7 @@ architecture behavioral of l2p_dma_master is

    -- Counter
    signal target_addr_cnt : std_logic_vector(31 downto 0) := (others => '0');
-    signal dma_length_cnt  : unsigned(12 downto 0)         := (others => '0');
+    signal dma_length_cnt  : unsigned(29 downto 0)         := (others => '0');
    signal l2p_timeout_cnt : unsigned(12 downto 0)         := (others => '0');

    -- Wishbone
@@ -325,7 +325,7 @@ begin
          l2p_last_packet <= '0';
        else
          if (l2p_dma_current_state = L2P_IDLE) then
-            l2p_len_cnt     <= unsigned(dma_ctrl_len_i(14 downto 2));
+            l2p_len_cnt     <= unsigned(dma_ctrl_len_i(31 downto 2));
            l2p_address_h   <= dma_ctrl_host_addr_h_i;
            l2p_address_l   <= dma_ctrl_host_addr_l_i;
            l2p_byte_swap   <= dma_ctrl_byte_swap_i;
@@ -340,8 +340,8 @@ begin
              l2p_len_header  <= TO_UNSIGNED(c_L2P_MAX_PAYLOAD, 13);
              l2p_last_packet <= '1';
            else
-              l2p_data_cnt    <= l2p_len_cnt;
-              l2p_len_header  <= l2p_len_cnt;
+              l2p_data_cnt    <= l2p_len_cnt(12 downto 0);
+              l2p_len_header  <= l2p_len_cnt(12 downto 0);
              l2p_last_packet <= '1';
            end if;
          elsif (l2p_dma_current_state = L2P_DATA) then
@@ -380,11 +380,11 @@ begin
            dma_length_cnt   <= (others => '0');
          elsif (dma_ctrl_start_l2p_i = '1') then
            if (l2p_dma_current_state = L2P_IDLE) then
-              -- dma target adrr is byte address, need 32bit address
+              -- dma target addr is byte address, need 32bit address
              target_addr_cnt(31 downto 30) <= "00";
              target_addr_cnt(29 downto 0)  <= dma_ctrl_target_addr_i(31 downto 2);
              -- dma target length is in byte, need 32bit
-              dma_length_cnt                <= unsigned(dma_ctrl_len_i(14 downto 2));
+              dma_length_cnt                <= unsigned(dma_ctrl_len_i(31 downto 2));
              dma_ctrl_error_o              <= '0';
            else
              target_addr_cnt  <= (others => '0');

--- a/hdl/sim/example_tb/main.sv
+++ b/hdl/sim/example_tb/main.sv
@@ -290,9 +290,9 @@ module main;
                ntest++, tests, i);

         // Restart
-         acc.write('h14, 'h4000); // count
+         acc.write('h14, 'h10000); // count
         acc.write('h20, 'h00); // attrib
-         acc.write('h0c, 'h20000000 + i * 'h1000); // hstartL
+         acc.write('h0c, 'h20000000 + i * 'h4000); // hstartL
         acc.write('h10, 'h00000000); // hstartH
         acc.write('h00, (i << 2) | 'h01); // start

@@ -300,7 +300,7 @@ module main;

         check_irq_status;

-         for (addr = 'h00; addr < 'h1000; addr += 1)
+         for (addr = 'h00; addr < 'h4000; addr += 1)
           begin
              expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
              if (i == 1)
@@ -309,8 +309,7 @@ module main;
                expected = {<<16{expected}};
              else if (i == 3)
                expected = {<<16{{<<8{expected}}}};
-              $display("ex: %x", expected);
-              mem_check((i * 'h1000) + 4 * addr, expected);
+              mem_check((i * 'h4000) + 4 * addr, expected);
           end

         clear_irq;