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Gennum GN4124 core
Commit b5752886 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: further reset and CDC cleanup 

Following up on 6c4dca2c, this commit fixes one issue related to resets and performs
further reset and clock-domain crossing (CDC) cleanup.

Important changes include:

1. Make sure that all dual async fifos are reset on both sides. This solves an issue
   with soft resets causing the host PC to hang.

2. Remove c_RST_ACTIVE constant to make the code simpler.

3. Remove reset from many signals (in particular from wide, data signals) that do not
   need to be reset. This helps with meeting timing wrt reset distribution.

4. Remove synchronizers from p2l deserializers, the SERDES outputs are already synced
   to the FPGA clock.
parent 3899b6ae
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Showing with 289 additions and 439 deletions
hdl/gn4124core/rtl/dma_controller.vhd
View file @ b5752886
......@@ -96,6 +96,11 @@ architecture behaviour of dma_controller is
-- Signals declaration
------------------------------------------------------------------------------
signal dma_ctrl_carrier_addr : std_logic_vector(31 downto 0) := (others => '0');
signal dma_ctrl_host_addr_h : std_logic_vector(31 downto 0) := (others => '0');
signal dma_ctrl_host_addr_l : std_logic_vector(31 downto 0) := (others => '0');
signal dma_ctrl_len : std_logic_vector(31 downto 0) := (others => '0');
-- DMA controller registers
signal dma_ctrl : std_logic_vector(31 downto 0);
signal dma_stat : std_logic_vector(31 downto 0);
......@@ -192,7 +197,7 @@ begin
p_regs : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = c_RST_ACTIVE) then
if (rst_n_i = '0') then
dma_ctrl_reg <= (others => '0');
dma_stat_reg <= (others => '0');
dma_cstart_reg <= (others => '0');
......@@ -270,12 +275,8 @@ begin
p_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = c_RST_ACTIVE) then
if(rst_n_i = '0') then
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
......@@ -312,12 +313,12 @@ begin
-- P2L transfer (from PCIe to target)
dma_ctrl_start_p2l_o <= '1';
end if;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_ctrl_carrier_addr_o <= dma_cstart_reg;
dma_ctrl_host_addr_h_o <= dma_hstarth_reg;
dma_ctrl_host_addr_l_o <= dma_hstartl_reg;
dma_ctrl_len_o <= dma_len_reg;
dma_status <= c_BUSY;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_ctrl_carrier_addr <= dma_cstart_reg;
dma_ctrl_host_addr_h <= dma_hstarth_reg;
dma_ctrl_host_addr_l <= dma_hstartl_reg;
dma_ctrl_len <= dma_len_reg;
dma_status <= c_BUSY;
end if;
when DMA_TRANSFER =>
......@@ -348,9 +349,9 @@ begin
when DMA_START_CHAIN =>
-- Catch the next item in host memory
dma_ctrl_current_state <= DMA_CHAIN;
dma_ctrl_host_addr_h_o <= dma_nexth_reg;
dma_ctrl_host_addr_l_o <= dma_nextl_reg;
dma_ctrl_len_o <= X"0000001C";
dma_ctrl_host_addr_h <= dma_nexth_reg;
dma_ctrl_host_addr_l <= dma_nextl_reg;
dma_ctrl_len <= X"0000001C";
dma_ctrl_start_next_o <= '1';
when DMA_CHAIN =>
......@@ -389,24 +390,28 @@ begin
end if;
when others =>
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= (others => '0');
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr <= (others => '0');
dma_ctrl_host_addr_h <= (others => '0');
dma_ctrl_host_addr_l <= (others => '0');
dma_ctrl_len <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= (others => '0');
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
end case;
end if;
end if;
end process p_fsm;
dma_ctrl_carrier_addr_o <= dma_ctrl_carrier_addr;
dma_ctrl_host_addr_h_o <= dma_ctrl_host_addr_h;
dma_ctrl_host_addr_l_o <= dma_ctrl_host_addr_l;
dma_ctrl_len_o <= dma_ctrl_len;
end behaviour;
hdl/gn4124core/rtl/l2p_arbiter.vhd
View file @ b5752886
......@@ -85,7 +85,7 @@ architecture rtl of l2p_arbiter is
signal eop : std_logic; -- End of packet
signal arb_ser_valid_t : std_logic;
signal arb_ser_dframe_t : std_logic;
signal arb_ser_data_t : std_logic_vector(31 downto 0);
signal arb_ser_data_t : std_logic_vector(31 downto 0) := (others => '0');
begin
......@@ -113,7 +113,7 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = c_RST_ACTIVE) then
if(rst_n_i = '0') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
......@@ -142,10 +142,9 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
arb_ser_valid_t <= '0';
arb_ser_dframe_t <= '0';
arb_ser_data_t <= (others => '0');
else
if arb_wbm_gnt = '1' then
arb_ser_valid_t <= wbm_arb_valid_i;
......@@ -171,10 +170,9 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
arb_ser_valid_o <= '0';
arb_ser_dframe_o <= '0';
arb_ser_data_o <= (others => '0');
else
arb_ser_valid_o <= arb_ser_valid_t;
arb_ser_dframe_o <= arb_ser_dframe_t;
......
hdl/gn4124core/rtl/l2p_dma_master.vhd
View file @ b5752886
This diff is collapsed.
hdl/gn4124core/rtl/p2l_decode32.vhd
View file @ b5752886
......@@ -91,8 +91,8 @@ architecture rtl of p2l_decode32 is
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
signal des_p2l_valid_d : std_logic;
signal des_p2l_dframe_d : std_logic;
signal des_p2l_valid_d : std_logic := '0';
signal des_p2l_dframe_d : std_logic := '0';
signal p2l_packet_start : std_logic;
signal p2l_packet_start_d : std_logic;
......@@ -101,23 +101,22 @@ architecture rtl of p2l_decode32 is
signal p2l_addr_cycle : std_logic;
signal p2l_data_cycle : std_logic;
signal p2l_hdr_strobe : std_logic; -- Indicates Header start cycle
signal p2l_hdr_length : std_logic_vector(9 downto 0); -- Latched LENGTH value from header
signal p2l_hdr_cid : std_logic_vector(1 downto 0); -- Completion ID
signal p2l_hdr_last : std_logic; -- Indicates Last packet in a completion
signal p2l_hdr_stat : std_logic_vector(1 downto 0); -- Completion Status
signal p2l_hdr_strobe : std_logic := '0'; -- Indicates Header start cycle
signal p2l_hdr_length : std_logic_vector(9 downto 0) := (others => '0'); -- Latched LENGTH value from header
signal p2l_hdr_cid : std_logic_vector(1 downto 0) := (others => '0'); -- Completion ID
signal p2l_hdr_last : std_logic := '0'; -- Indicates Last packet in a completion
signal p2l_hdr_stat : std_logic_vector(1 downto 0) := (others => '0'); -- Completion Status
signal p2l_hdr_fbe : std_logic_vector(3 downto 0) := (others => '0'); -- First Byte Enable
signal p2l_hdr_lbe : std_logic_vector(3 downto 0) := (others => '0'); -- Last Byte Enable
signal p2l_addr_start : std_logic;
signal p2l_addr : unsigned(31 downto 0); -- Registered and counting Address
signal p2l_addr : unsigned(31 downto 0) := (others => '0'); -- Registered and counting Address
signal p2l_d_valid : std_logic; -- Indicates Address/Data is valid
signal p2l_d_valid : std_logic; -- Indicates Address/Data is valid
signal p2l_d_first : std_logic;
signal p2l_d_last : std_logic; -- Indicates end of the packet
signal p2l_d : std_logic_vector(31 downto 0); -- Address/Data
signal p2l_be : std_logic_vector(3 downto 0); -- Byte Enable for data
signal p2l_hdr_fbe : std_logic_vector(3 downto 0); -- First Byte Enable
signal p2l_hdr_lbe : std_logic_vector(3 downto 0); -- Last Byte Enable
signal p2l_d_last : std_logic; -- Indicates end of the packet
signal p2l_d : std_logic_vector(31 downto 0) := (others => '0'); -- Address/Data
signal p2l_be : std_logic_vector(3 downto 0) := (others => '0'); -- Byte Enable for data
signal target_mrd : std_logic;
signal target_mwr : std_logic;
......@@ -135,13 +134,8 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
des_p2l_dframe_d <= '0';
des_p2l_valid_d <= '0';
else
des_p2l_dframe_d <= des_p2l_dframe_i;
des_p2l_valid_d <= des_p2l_valid_i;
end if;
des_p2l_dframe_d <= des_p2l_dframe_i;
des_p2l_valid_d <= des_p2l_valid_i;
end if;
end process;
......@@ -157,7 +151,7 @@ begin
p_type_decode : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
target_mrd <= '0';
target_mwr <= '0';
master_cpld <= '0';
......@@ -189,12 +183,10 @@ begin
p_header_decode : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
p2l_hdr_strobe <= '0';
p2l_hdr_length <= (others => '0');
p2l_hdr_cid <= (others => '0');
p2l_hdr_last <= '0';
p2l_hdr_stat <= (others => '0');
p2l_hdr_fbe <= (others => '0');
p2l_hdr_lbe <= (others => '0');
else
......@@ -224,9 +216,8 @@ begin
p_addr_decode : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
p2l_addr_cycle <= '0';
p2l_addr <= (others => '0');
p2l_addr_start <= '0';
else
-- Indicate address cycle(s)
......@@ -269,11 +260,10 @@ begin
p_data_decode : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
p2l_data_cycle <= '0';
p2l_d_valid <= '0';
p2l_d_last <= '0';
p2l_d <= (others => '0');
else
-- Indicates data cycle(s)
-- Data cycle comes after an address cycle, exept for read completion packet
......@@ -306,7 +296,7 @@ begin
p_be_decode : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = c_RST_ACTIVE then
if rst_n_i = '0' then
p2l_be <= (others => '0');
else
if (p2l_addr_start = '1') then
......
hdl/gn4124core/rtl/p2l_dma_master.vhd
View file @ b5752886
This diff is collapsed.
hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
View file @ b5752886
......@@ -153,11 +153,7 @@ architecture rtl of gn4124_core is
attribute keep of io_clk : signal is "TRUE";
-- Reset for all clk_p logic
signal rst_reg : std_logic;
signal rst_reg_d : std_logic;
signal rst : std_logic;
signal rst_n : std_logic;
signal rst_sync_n : std_logic;
signal sys_rst_n : std_logic;
signal arst_pll : std_logic;
-------------------------------------------------------------
......@@ -333,33 +329,17 @@ begin
------------------------------------------------------------------------------
-- Reset aligned to core clock
------------------------------------------------------------------------------
p_core_rst : process (sys_clk, rst_n_a_i)
begin
if rst_n_a_i = c_RST_ACTIVE then
rst_reg <= c_RST_ACTIVE;
elsif rising_edge(sys_clk) then
rst_reg_d <= rst_reg;
if p2l_pll_locked = '1' then
rst_reg <= not(c_RST_ACTIVE);
end if;
end if;
end process p_core_rst;
rst_n <= rst_reg_d;
cmp_core_rst_sync: gc_sync_ffs
port map (
clk_i => sys_clk,
rst_n_i => rst_n_a_i,
data_i => p2l_pll_locked,
synced_o => sys_rst_n);
-- Always active high reset for PLL
-- Always active high reset for PLL and SERDES
arst_pll <= not(rst_n_a_i);
-- Always active low sys reset for synchronizers
gen_sync_rst_n : if c_RST_ACTIVE = '0' generate
rst_sync_n <= rst_n;
end generate;
gen_sync_rst : if c_RST_ACTIVE = '1' generate
rst_sync_n <= not rst_n;
end generate;
------------------------------------------------------------------------------
-- IRQ pulse forward to GN4124 GPIO
------------------------------------------------------------------------------
......@@ -377,7 +357,7 @@ begin
(
---------------------------------------------------------
-- Clocks and reset
rst_n_i => rst_n,
rst_a_i => arst_pll,
sys_clk_i => sys_clk,
io_clk_i => io_clk,
serdes_strobe_i => serdes_strobe,
......@@ -410,7 +390,7 @@ begin
---------------------------------------------------------
-- Clock/Reset
clk_i => sys_clk,
rst_n_i => rst_n,
rst_n_i => sys_rst_n,
---------------------------------------------------------
-- Input from the Deserializer
......@@ -461,7 +441,7 @@ begin
---------------------------------------------------------
-- Clock/Reset
clk_i => sys_clk,
rst_n_i => rst_n,
rst_n_i => sys_rst_n,
---------------------------------------------------------
-- From P2L Decoder
......@@ -524,7 +504,7 @@ begin
port map
(
clk_i => sys_clk,
rst_n_i => rst_n,
rst_n_i => sys_rst_n,
dma_ctrl_irq_o => dma_irq,
......@@ -573,7 +553,7 @@ begin
cmp_dma_irq_sync : gc_pulse_synchronizer2
port map(
clk_in_i => sys_clk,
rst_in_n_i => rst_sync_n,
rst_in_n_i => sys_rst_n,
clk_out_i => csr_clk_i,
rst_out_n_i => csr_rst_n_i,
d_p_i => dma_irq(I),
......@@ -589,7 +569,7 @@ begin
port map
(
clk_i => sys_clk,
rst_n_i => rst_n,
rst_n_i => sys_rst_n,
dma_ctrl_target_addr_i => dma_ctrl_carrier_addr,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h,
......@@ -633,7 +613,7 @@ begin
port map
(
clk_i => sys_clk,
rst_n_i => rst_n,
rst_n_i => sys_rst_n,
dma_ctrl_carrier_addr_i => dma_ctrl_carrier_addr,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h,
......@@ -741,7 +721,7 @@ begin
cmp_sync_l_wr_rdy : gc_sync_ffs
port map (
clk_i => sys_clk,
rst_n_i => rst_sync_n,
rst_n_i => sys_rst_n,
data_i => l_wr_rdy_t,
synced_o => l_wr_rdy);
......@@ -752,7 +732,7 @@ begin
cmp_sync_p_rd_d_rdy : gc_sync_ffs
port map (
clk_i => sys_clk,
rst_n_i => rst_sync_n,
rst_n_i => sys_rst_n,
data_i => p_rd_d_rdy_t,
synced_o => p_rd_d_rdy);
......@@ -761,7 +741,7 @@ begin
cmp_sync_l2p_rdy : gc_sync_ffs
port map (
clk_i => sys_clk,
rst_n_i => rst_sync_n,
rst_n_i => sys_rst_n,
data_i => l2p_rdy_i,
synced_o => l2p_rdy);
......@@ -770,7 +750,7 @@ begin
cmp_sync_tx_error : gc_sync_ffs
port map (
clk_i => sys_clk,
rst_n_i => rst_sync_n,
rst_n_i => sys_rst_n,
data_i => tx_error_i,
synced_o => tx_error);
......@@ -782,7 +762,7 @@ begin
p_l2p_edb_d3 : process (sys_clk) is
begin
if rising_edge(sys_clk) then
if rst_n = c_RST_ACTIVE then
if sys_rst_n = '0' then
l2p_edb_d1 <= '0';
l2p_edb_d2 <= '0';
else
......@@ -802,7 +782,7 @@ begin
---------------------------------------------------------
-- Clock/Reset
clk_i => sys_clk,
rst_n_i => rst_n,
rst_n_i => sys_rst_n,
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
......@@ -845,7 +825,7 @@ begin
(
---------------------------------------------------------
-- Clocks and reset
rst_n_i => rst_n,
rst_a_i => arst_pll,
sys_clk_i => sys_clk,
io_clk_i => io_clk,
serdes_strobe_i => serdes_strobe,
......
hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
View file @ b5752886
......@@ -40,12 +40,6 @@ use work.wishbone_pkg.all;
package gn4124_core_pkg is
--==============================================================================
--! Constants declaration
--==============================================================================
constant c_RST_ACTIVE : std_logic := '0'; -- Active low reset
--==============================================================================
--! Functions declaration
--==============================================================================
......@@ -55,8 +49,6 @@ package gn4124_core_pkg is
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
......@@ -255,18 +247,4 @@ package body gn4124_core_pkg is
return dout;
end function f_byte_swap;
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end gn4124_core_pkg;
hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
View file @ b5752886
......@@ -37,7 +37,7 @@ entity l2p_ser is
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
rst_a_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
......@@ -103,9 +103,6 @@ architecture rtl of l2p_ser is
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal l2p_dframe_t : std_logic_vector(1 downto 0);
signal l2p_valid_t : std_logic_vector(1 downto 0);
......@@ -118,17 +115,6 @@ architecture rtl of l2p_ser is
begin
------------------------------------------------------------------------------
-- Active high reset for DDR FF
------------------------------------------------------------------------------
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- Instantiate serialiser to generate forwarded clock
------------------------------------------------------------------------------
......@@ -140,7 +126,7 @@ begin
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
reset => rst_a_i,
datain => c_TX_CLK, -- Transmit a constant to make the clock
dataout_p => l2p_clk_p_v,
dataout_n => l2p_clk_n_v);
......@@ -160,7 +146,7 @@ begin
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
reset => rst_a_i,
datain => l2p_data_i,
dataout => l2p_data_o);
......@@ -175,7 +161,7 @@ begin
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
reset => rst_a_i,
datain => l2p_dframe_t,
dataout => l2p_dframe_v);
......@@ -196,7 +182,7 @@ begin
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
reset => rst_a_i,
datain => l2p_valid_t,
dataout => l2p_valid_v);
......
hdl/gn4124core/rtl/spartan6/p2l_des.vhd
View file @ b5752886
......@@ -37,7 +37,7 @@ entity p2l_des is
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
rst_a_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
......@@ -96,55 +96,13 @@ architecture rtl of p2l_des is
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal p2l_valid_v : std_logic_vector(0 downto 0);
signal p2l_dframe_v : std_logic_vector(0 downto 0);
signal p2l_valid_t : std_logic_vector(1 downto 0);
signal p2l_dframe_t : std_logic_vector(1 downto 0);
signal p2l_data_t : std_logic_vector(p2l_data_o'range);
signal p2l_valid_t2 : std_logic;
signal p2l_dframe_t2 : std_logic;
signal p2l_data_t2 : std_logic_vector(p2l_data_o'range);
signal p2l_data_bitslip : std_logic_vector(1 downto 0);
signal p2l_data_bitslip_p : std_logic;
--signal p2l_ctrl_v : std_logic_vector(1 downto 0);
--signal p2l_ctrl_t : std_logic_vector(3 downto 0);
signal p2l_valid_t : std_logic_vector(1 downto 0) := (others => '0');
signal p2l_dframe_t : std_logic_vector(1 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
gen_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- data input bit slip
------------------------------------------------------------------------------
p_din_bitslip : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if rst_n_i = c_RST_ACTIVE then
p2l_data_bitslip <= (others => '0');
else
p2l_data_bitslip <= p2l_data_bitslip(0) & '1';
end if;
end if;
end process p_din_bitslip;
p2l_data_bitslip_p <= p2l_data_bitslip(0) and not(p2l_data_bitslip(1));
------------------------------------------------------------------------------
-- data inputs
------------------------------------------------------------------------------
......@@ -159,9 +117,9 @@ begin
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0', --p2l_data_bitslip_p,
reset => rst,
data_out => p2l_data_t,
bitslip => '0',
reset => rst_a_i,
data_out => p2l_data_o,
debug_in => "00",
debug => open);
......@@ -175,18 +133,17 @@ begin
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_dframe_v,
datain(0) => p2l_dframe_i,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
reset => rst_a_i,
data_out => p2l_dframe_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_dframe_v(0) <= p2l_dframe_i;
p2l_dframe_o <= p2l_dframe_t(0);
------------------------------------------------------------------------------
-- valid input
......@@ -198,41 +155,16 @@ begin
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_valid_v,
datain(0) => p2l_valid_i,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
reset => rst_a_i,
data_out => p2l_valid_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_valid_v(0) <= p2l_valid_i;
p_in_sys_sync : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if rst_n_i = c_RST_ACTIVE then
p2l_data_o <= (others => '0');
p2l_dframe_o <= '0';
p2l_valid_o <= '0';
p2l_data_t2 <= (others => '0');
p2l_dframe_t2 <= '0';
p2l_valid_t2 <= '0';
else
p2l_data_t2 <= p2l_data_t;
p2l_dframe_t2 <= p2l_dframe_t(0);
p2l_valid_t2 <= p2l_valid_t(0);
p2l_data_o <= p2l_data_t2;
p2l_dframe_o <= p2l_dframe_t2;
p2l_valid_o <= p2l_valid_t2;
end if;
end if;
end process p_in_sys_sync;
p2l_valid_o <= p2l_valid_t(0);
end rtl;
hdl/gn4124core/rtl/wbmaster32.vhd
View file @ b5752886
......@@ -27,6 +27,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
......@@ -111,13 +112,14 @@ architecture behaviour of wbmaster32 is
-----------------------------------------------------------------------------
-- Sync fifos
signal fifo_rst_n : std_logic;
signal fifo_rst_n : std_logic;
signal wb_fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
signal to_wb_fifo_rd : std_logic;
signal to_wb_fifo_wr : std_logic;
signal to_wb_fifo_din : std_logic_vector(65 downto 0);
signal to_wb_fifo_din : std_logic_vector(65 downto 0) := (others => '0');
signal to_wb_fifo_dout : std_logic_vector(65 downto 0);
signal to_wb_fifo_rw : std_logic;
signal to_wb_fifo_data : std_logic_vector(31 downto 0);
......@@ -128,9 +130,11 @@ architecture behaviour of wbmaster32 is
signal from_wb_fifo_full : std_logic;
signal from_wb_fifo_rd : std_logic;
signal from_wb_fifo_wr : std_logic;
signal from_wb_fifo_din : std_logic_vector(33 downto 0);
signal from_wb_fifo_din : std_logic_vector(33 downto 0) := (others => '0');
signal from_wb_fifo_dout : std_logic_vector(33 downto 0);
signal wbm_arb_data : std_logic_vector(31 downto 0) := (others => '0');
-- Wishbone
type wishbone_state_type is (WB_IDLE, WB_READ_FIFO, WB_CYCLE, WB_WAIT_ACK);
signal wishbone_current_state : wishbone_state_type;
......@@ -139,11 +143,11 @@ architecture behaviour of wbmaster32 is
signal wb_err_t : std_logic;
signal wb_dat_i_t : std_logic_vector(31 downto 0);
signal wb_cyc_t : std_logic;
signal wb_dat_o_t : std_logic_vector(31 downto 0);
signal wb_dat_o_t : std_logic_vector(31 downto 0) := (others => '0');
signal wb_stb_t : std_logic;
signal wb_adr_t : std_logic_vector(30 downto 0);
signal wb_adr_t : std_logic_vector(30 downto 0) := (others => '0');
signal wb_we_t : std_logic;
signal wb_sel_t : std_logic_vector(3 downto 0);
signal wb_sel_t : std_logic_vector(3 downto 0) := (others => '0');
signal wb_stall_t : std_logic;
signal wb_cid_t : std_logic_vector(1 downto 0);
......@@ -162,16 +166,18 @@ begin
------------------------------------------------------------------------------
-- Active low reset for fifos
-- Active low resets for fifos
------------------------------------------------------------------------------
-- Creates an active low reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst_n <= rst_n_i;
end generate;
fifo_rst_n <= rst_n_i;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst_n <= not(rst_n_i);
end generate;
-- Local resynced copy of fifo_rst_n to make sure that both sides of the fifo
-- are reset if rst_n_i = '0'
cmp_wb_fifo_rst_sync: gc_sync_ffs
port map (
clk_i => wb_clk_i,
rst_n_i => wb_rst_n_i,
data_i => fifo_rst_n,
synced_o => wb_fifo_rst_n);
------------------------------------------------------------------------------
-- Write frame from P2L decoder to fifo
......@@ -186,8 +192,7 @@ begin
p_from_decoder : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = c_RST_ACTIVE) then
to_wb_fifo_din <= (others => '0');
if (rst_n_i = '0') then
to_wb_fifo_wr <= '0';
else
if (pd_wbm_target_mwr_i = '1' and pd_wbm_data_valid_i = '1') then
......@@ -233,7 +238,7 @@ begin
& p2l_cid --> CID (Completion Identifer)
& "0000000001"; --> Length (Single 32-bit word read only)
p2l_cid <= from_wb_fifo_dout(33 downto 32);
------------------------------------------------------------------------------
......@@ -247,14 +252,13 @@ begin
from_wb_fifo_rd <= '0';
end if;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = c_RST_ACTIVE) then
if(rst_n_i = '0') then
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_req_o <= '0';
wbm_arb_data_o <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
else
......@@ -262,7 +266,7 @@ begin
when L2P_IDLE =>
wbm_arb_req_o <= '0';
wbm_arb_data_o <= (others => '0');
wbm_arb_data <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
if(from_wb_fifo_empty = '0' and p_rd_d_rdy_i = '1') then
......@@ -277,7 +281,7 @@ begin
if(arb_wbm_gnt_i = '1') then
wbm_arb_req_o <= '0';
wbm_arb_data_o <= s_l2p_header;
wbm_arb_data <= s_l2p_header;
wbm_arb_valid_o <= '1';
wbm_arb_dframe_o <= '1';
l2p_read_cpl_current_state <= L2P_DATA;
......@@ -285,13 +289,13 @@ begin
when L2P_DATA =>
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_data_o <= from_wb_fifo_dout(31 downto 0);
wbm_arb_data <= from_wb_fifo_dout(31 downto 0);
wbm_arb_dframe_o <= '0';
when others =>
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_req_o <= '0';
wbm_arb_data_o <= (others => '0');
wbm_arb_data <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
......@@ -300,6 +304,8 @@ begin
end if;
end process;
wbm_arb_data_o <= wbm_arb_data;
-----------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
-----------------------------------------------------------------------------
......@@ -332,7 +338,7 @@ begin
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
rst_rd_n_i => wb_rst_n_i,
rst_rd_n_i => wb_fifo_rst_n,
clk_rd_i => wb_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
......@@ -366,7 +372,7 @@ begin
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_FROM_WB_FIFO_FULL_THRES)
port map (
rst_wr_n_i => wb_rst_n_i,
rst_wr_n_i => wb_fifo_rst_n,
clk_wr_i => wb_clk_i,
d_i => from_wb_fifo_din,
we_i => from_wb_fifo_wr,
......@@ -391,16 +397,12 @@ begin
p_wb_fsm : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if(wb_rst_n_i = '0') then
if wb_fifo_rst_n = '0' then
wishbone_current_state <= WB_IDLE;
to_wb_fifo_rd <= '0';
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_we_t <= '0';
wb_sel_t <= "0000";
wb_dat_o_t <= (others => '0');
wb_adr_t <= (others => '0');
from_wb_fifo_din <= (others => '0');
from_wb_fifo_wr <= '0';
else
case wishbone_current_state is
......@@ -499,7 +501,7 @@ begin
p_wb_ack_timeout_cnt : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_n_i = '0' then
if wb_fifo_rst_n = '0' then
wb_ack_timeout_cnt <= (others => '1');
else
if wishbone_current_state = WB_WAIT_ACK then
......@@ -516,7 +518,7 @@ begin
p_ack_timeout : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_n_i = '0' then
if wb_fifo_rst_n = '0' then
wb_ack_timeout <= '0';
else
if wb_ack_timeout_cnt = 0 then
......@@ -529,4 +531,3 @@ begin
end process p_ack_timeout;
end behaviour;
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