[hdl] update and expand example testbench

3159ffcd · Dimitris Lampridis · dcf190ed · 3159ffcd · 3159ffcd
Commit 3159ffcd authored Aug 08, 2019 by Dimitris Lampridis
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Showing with 38 additions and 4 deletions

main.sv hdl/sim/example_tb/main.sv +37 -3

run.do hdl/sim/example_tb/run.do +1 -1

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--- a/hdl/sim/example_tb/main.sv
+++ b/hdl/sim/example_tb/main.sv
@@ -142,7 +142,7 @@ module main;

      @(posedge clk_125m);

-      $write("Test 1/3: simple read/write accesses over Wishbone: ");
+      $write("Test 1/4: simple read/write accesses over Wishbone: ");

      // Verify simple read/writes over wishbone
      reg_check('h0, 'h0);
@@ -161,7 +161,7 @@ module main;

      $write("PASS\n");

-      $write("Test 2/3: 32 reads over DMA, abort after first read: ");
+      $write("Test 2/4: 32 reads over DMA, abort after first read: ");

      // Perform 32 reads over DMA
      reg_check('h00, 'h00000000);
@@ -193,7 +193,7 @@ module main;

      $write("PASS\n");

-      $write("Test 3/3: 32 reads over DMA: ");
+      $write("Test 3/4: 32 reads over DMA: ");

      // Restart
      acc.write('h14, 'h80); // count
@@ -227,6 +227,40 @@ module main;

      $write("PASS\n");

+      $write("Test 4/4: 16 reads over DMA: ");
+
+      // Restart
+      acc.write('h14, 'h40); // count
+      acc.write('h00, 'h01); // start
+
+      @(posedge i_gn4124.l2p_valid); // skip header
+      @(posedge i_gn4124.l2p_valid);
+
+      for (addr = 'h20; addr > 'h10; addr -= 1)
+        begin
+           expected = 64'h80000000 + addr - 1;
+           val = i_gn4124.l2p_data;
+           @(posedge i_gn4124.l2p_clk_n);
+           val |= i_gn4124.l2p_data << 16;
+           val_check("DMA read-back", 'h20-addr, val, expected);
+           @(posedge i_gn4124.l2p_clk_p);
+        end
+
+      repeat(4) @(posedge clk_125m);
+
+      //  Check irq status
+      reg_check('h04, 'h04);
+      if (dma_irq != 1'b1)
+        $fatal(1, "dma irq should be 1");
+
+      // clear irq
+      acc.write('h04, 'h04);
+      reg_check('h04, 'h00);
+      if (dma_irq != 1'b0)
+        $fatal(1, "dma irq should be 0");
+
+      $write("PASS\n");
+
      #1us;

      $display();

--- a/hdl/sim/example_tb/run.do
+++ b/hdl/sim/example_tb/run.do
-vsim -quiet -L unisim work.main
+vsim -quiet -L unisim  -classdebug -voptargs=+acc work.main

 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1