Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
G
Gennum GN4124 core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Gennum GN4124 core
Commits
0284a69b
Commit
0284a69b
authored
Jul 03, 2020
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: DMA rewrite work-in-progress.
parent
f1e9a982
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
9 changed files
with
428 additions
and
359 deletions
+428
-359
general-cores
hdl/ip_cores/general-cores
+1
-1
l2p_dma_master.vhd
hdl/rtl/l2p_dma_master.vhd
+100
-105
p2l_dma_master.vhd
hdl/rtl/p2l_dma_master.vhd
+127
-98
gn4124_core.vhd
hdl/rtl/spartan6/gn4124_core.vhd
+27
-52
gn4124_core_pkg.vhd
hdl/rtl/spartan6/gn4124_core_pkg.vhd
+4
-6
xwb_gn4124_core.vhd
hdl/rtl/spartan6/xwb_gn4124_core.vhd
+3
-5
main.sv
hdl/sim/example_tb/main.sv
+107
-42
mem_init.bram
hdl/sim/example_tb/mem_init.bram
+0
-32
wave.do
hdl/sim/example_tb/wave.do
+59
-18
No files found.
general-cores
@
b9925c97
Subproject commit
64f7e518bab2bf0489077f4b9eb26e8cccbf141
1
Subproject commit
b9925c97707698310e232ae2736e3d3d4b1b597
1
hdl/rtl/l2p_dma_master.vhd
View file @
0284a69b
This diff is collapsed.
Click to expand it.
hdl/rtl/p2l_dma_master.vhd
View file @
0284a69b
This diff is collapsed.
Click to expand it.
hdl/rtl/spartan6/gn4124_core.vhd
View file @
0284a69b
...
...
@@ -52,9 +52,8 @@ entity gn4124_core is
g_WBM_TO_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_WBM_FROM_WB_FIFO_SIZE
:
positive
:
=
128
;
g_WBM_FROM_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_P2L_FIFO_SIZE
:
positive
:
=
512
;
g_P2L_FIFO_FULL_THRES
:
positive
:
=
500
;
g_L2P_DATA_FIFO_SIZE
:
positive
:
=
128
;
g_P2L_FIFO_SIZE
:
positive
:
=
64
;
g_L2P_FIFO_SIZE
:
positive
:
=
128
;
-- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT
:
positive
:
=
100
);
port
(
...
...
@@ -289,19 +288,6 @@ architecture rtl of gn4124_core is
signal
dma_irq
:
std_logic
;
attribute
keep
of
dma_ctrl_l2p_error
:
signal
is
"TRUE"
;
attribute
keep
of
dma_ctrl_l2p_done
:
signal
is
"TRUE"
;
attribute
keep
of
dma_ctrl_start_l2p
:
signal
is
"TRUE"
;
attribute
keep
of
dma_ctrl_abort
:
signal
is
"TRUE"
;
attribute
keep
of
ldm_arb_valid
:
signal
is
"TRUE"
;
attribute
keep
of
ldm_arb_dframe
:
signal
is
"TRUE"
;
attribute
keep
of
ldm_arb_data
:
signal
is
"TRUE"
;
attribute
keep
of
ldm_arb_req
:
signal
is
"TRUE"
;
attribute
keep
of
l2p_rdy
:
signal
is
"TRUE"
;
attribute
keep
of
l_wr_rdy
:
signal
is
"TRUE"
;
attribute
keep
of
tx_error
:
signal
is
"TRUE"
;
attribute
keep
of
arb_ldm_gnt
:
signal
is
"TRUE"
;
------------------------------------------------------------------------------
-- CSR wishbone bus
------------------------------------------------------------------------------
...
...
@@ -313,14 +299,8 @@ architecture rtl of gn4124_core is
signal
l2p_dma_in
:
t_wishbone_master_in
;
signal
l2p_dma_out
:
t_wishbone_master_out
;
signal
p2l_dma_adr
:
std_logic_vector
(
31
downto
0
);
signal
p2l_dma_dat
:
std_logic_vector
(
31
downto
0
);
signal
p2l_dma_sel
:
std_logic_vector
(
3
downto
0
);
signal
p2l_dma_cyc
:
std_logic
;
signal
p2l_dma_stb
:
std_logic
;
signal
p2l_dma_we
:
std_logic
;
signal
p2l_dma_ack
:
std_logic
;
signal
p2l_dma_stall
:
std_logic
;
signal
p2l_dma_in
:
t_wishbone_master_in
;
signal
p2l_dma_out
:
t_wishbone_master_out
;
--==============================================================================
-- Architecture begin (gn4124_core)
...
...
@@ -619,7 +599,7 @@ begin
cmp_l2p_dma_master
:
entity
work
.
l2p_dma_master
generic
map
(
g_DMA_USE_PCI_CLK
=>
g_DMA_USE_PCI_CLK
,
g_
DATA_FIFO_SIZE
=>
g_L2P_DATA
_FIFO_SIZE
,
g_
FIFO_SIZE
=>
g_L2P
_FIFO_SIZE
,
g_BYTE_SWAP
=>
TRUE
)
port
map
(
clk_i
=>
sys_clk
,
...
...
@@ -660,10 +640,9 @@ begin
-----------------------------------------------------------------------------
cmp_p2l_dma_master
:
entity
work
.
p2l_dma_master
generic
map
(
--g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE
=>
g_P2L_FIFO_SIZE
,
g_FIFO_FULL_THRES
=>
g_P2L_FIFO_FULL_THRES
,
g_BYTE_SWAP
=>
TRUE
)
g_DMA_USE_PCI_CLK
=>
g_DMA_USE_PCI_CLK
,
g_FIFO_SIZE
=>
g_P2L_FIFO_SIZE
,
g_BYTE_SWAP
=>
TRUE
)
port
map
(
clk_i
=>
sys_clk
,
rst_n_i
=>
sys_rst_n
,
...
...
@@ -699,17 +678,10 @@ begin
pdm_arb_req_o
=>
pdm_arb_req
,
arb_pdm_gnt_i
=>
arb_pdm_gnt
,
p2l_dma_rst_n_i
=>
dma_rst_n_i
,
p2l_dma_clk_i
=>
dma_clk_i
,
p2l_dma_adr_o
=>
p2l_dma_adr
,
p2l_dma_dat_i
=>
dma_dat_i
,
p2l_dma_dat_o
=>
p2l_dma_dat
,
p2l_dma_sel_o
=>
p2l_dma_sel
,
p2l_dma_cyc_o
=>
p2l_dma_cyc
,
p2l_dma_stb_o
=>
p2l_dma_stb
,
p2l_dma_we_o
=>
p2l_dma_we
,
p2l_dma_ack_i
=>
p2l_dma_ack
,
p2l_dma_stall_i
=>
p2l_dma_stall
,
wb_dma_rst_n_i
=>
wb_dma_rst_n
,
wb_dma_clk_i
=>
wb_dma_clk
,
wb_dma_i
=>
p2l_dma_in
,
wb_dma_o
=>
p2l_dma_out
,
next_item_carrier_addr_o
=>
next_item_carrier_addr
,
next_item_host_addr_h_o
=>
next_item_host_addr_h
,
...
...
@@ -721,9 +693,12 @@ begin
next_item_valid_o
=>
next_item_valid
);
p2l_dma_in
.
dat
<=
dma_dat_i
;
p2l_dma_in
.
err
<=
dma_err_i
;
p2l_dma_in
.
rty
<=
dma_rty_i
;
p_dma_wb_mux
:
process
(
dma_ack_i
,
dma_ctrl_direction
,
dma_stall_i
,
l2p_dma_out
,
p2l_dma_adr
,
p2l_dma_cyc
,
p2l_dma_dat
,
p2l_dma_sel
,
p2l_dma_stb
,
p2l_dma_we
)
l2p_dma_out
,
p2l_dma_out
)
begin
if
(
dma_ctrl_direction
=
'0'
)
then
dma_adr_o
<=
l2p_dma_out
.
adr
;
...
...
@@ -734,17 +709,17 @@ begin
dma_we_o
<=
l2p_dma_out
.
we
;
l2p_dma_in
.
ack
<=
dma_ack_i
;
l2p_dma_in
.
stall
<=
dma_stall_i
;
p2l_dma_
ack
<=
'0'
;
p2l_dma_
stall
<=
'0'
;
p2l_dma_
in
.
ack
<=
'0'
;
p2l_dma_
in
.
stall
<=
'0'
;
else
dma_adr_o
<=
p2l_dma_adr
;
dma_dat_o
<=
p2l_dma_dat
;
dma_sel_o
<=
p2l_dma_sel
;
dma_cyc_o
<=
p2l_dma_cyc
;
dma_stb_o
<=
p2l_dma_stb
;
dma_we_o
<=
p2l_dma_we
;
p2l_dma_
ack
<=
dma_ack_i
;
p2l_dma_
stall
<=
dma_stall_i
;
dma_adr_o
<=
p2l_dma_
out
.
adr
;
dma_dat_o
<=
p2l_dma_
out
.
dat
;
dma_sel_o
<=
p2l_dma_
out
.
sel
;
dma_cyc_o
<=
p2l_dma_
out
.
cyc
;
dma_stb_o
<=
p2l_dma_
out
.
stb
;
dma_we_o
<=
p2l_dma_
out
.
we
;
p2l_dma_
in
.
ack
<=
dma_ack_i
;
p2l_dma_
in
.
stall
<=
dma_stall_i
;
l2p_dma_in
.
ack
<=
'0'
;
l2p_dma_in
.
stall
<=
'0'
;
end
if
;
...
...
hdl/rtl/spartan6/gn4124_core_pkg.vhd
View file @
0284a69b
...
...
@@ -61,9 +61,8 @@ package gn4124_core_pkg is
g_WBM_TO_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_WBM_FROM_WB_FIFO_SIZE
:
positive
:
=
128
;
g_WBM_FROM_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_P2L_FIFO_SIZE
:
positive
:
=
512
;
g_P2L_FIFO_FULL_THRES
:
positive
:
=
500
;
g_L2P_DATA_FIFO_SIZE
:
positive
:
=
128
;
g_P2L_FIFO_SIZE
:
positive
:
=
64
;
g_L2P_FIFO_SIZE
:
positive
:
=
128
;
g_WB_MASTER_MODE
:
t_wishbone_interface_mode
:
=
PIPELINED
;
g_WB_MASTER_GRANULARITY
:
t_wishbone_address_granularity
:
=
BYTE
;
g_WB_DMA_CFG_MODE
:
t_wishbone_interface_mode
:
=
PIPELINED
;
...
...
@@ -122,9 +121,8 @@ package gn4124_core_pkg is
g_WBM_TO_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_WBM_FROM_WB_FIFO_SIZE
:
positive
:
=
128
;
g_WBM_FROM_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_P2L_FIFO_SIZE
:
positive
:
=
512
;
g_P2L_FIFO_FULL_THRES
:
positive
:
=
500
;
g_L2P_DATA_FIFO_SIZE
:
positive
:
=
128
;
g_P2L_FIFO_SIZE
:
positive
:
=
64
;
g_L2P_FIFO_SIZE
:
positive
:
=
128
;
g_ACK_TIMEOUT
:
positive
:
=
100
);
port
(
---------------------------------------------------------
...
...
hdl/rtl/spartan6/xwb_gn4124_core.vhd
View file @
0284a69b
...
...
@@ -45,9 +45,8 @@ entity xwb_gn4124_core is
g_WBM_TO_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_WBM_FROM_WB_FIFO_SIZE
:
positive
:
=
128
;
g_WBM_FROM_WB_FIFO_FULL_THRES
:
positive
:
=
110
;
g_P2L_FIFO_SIZE
:
positive
:
=
512
;
g_P2L_FIFO_FULL_THRES
:
positive
:
=
500
;
g_L2P_DATA_FIFO_SIZE
:
positive
:
=
128
;
g_P2L_FIFO_SIZE
:
positive
:
=
64
;
g_L2P_FIFO_SIZE
:
positive
:
=
128
;
-- WB config for three WB interfaces
g_WB_MASTER_MODE
:
t_wishbone_interface_mode
:
=
PIPELINED
;
g_WB_MASTER_GRANULARITY
:
t_wishbone_address_granularity
:
=
BYTE
;
...
...
@@ -204,8 +203,7 @@ begin
g_WBM_FROM_WB_FIFO_SIZE
=>
g_WBM_FROM_WB_FIFO_SIZE
,
g_WBM_FROM_WB_FIFO_FULL_THRES
=>
g_WBM_FROM_WB_FIFO_FULL_THRES
,
g_P2L_FIFO_SIZE
=>
g_P2L_FIFO_SIZE
,
g_P2L_FIFO_FULL_THRES
=>
g_P2L_FIFO_FULL_THRES
,
g_L2P_DATA_FIFO_SIZE
=>
g_L2P_DATA_FIFO_SIZE
,
g_L2P_FIFO_SIZE
=>
g_L2P_FIFO_SIZE
,
g_ACK_TIMEOUT
=>
g_ACK_TIMEOUT
)
port
map
(
rst_n_a_i
=>
rst_n_a_i
,
...
...
hdl/sim/example_tb/main.sv
View file @
0284a69b
...
...
@@ -54,13 +54,13 @@ module main;
logic
wb_dma_clk
;
logic
wb_dma_rst_n
;
initial
begin
rst_125m_n
=
0
;
rst_62m5_n
=
0
;
rst_62m5_n
=
0
;
#
80
ns
;
rst_125m_n
=
1
;
rst_62m5_n
=
1
;
rst_62m5_n
=
1
;
end
IGN4124PCIMaster
i_gn4124
()
;
...
...
@@ -71,8 +71,8 @@ module main;
)
DUT
(
.
rst_n_a_i
(
i_gn4124
.
rst_n
)
,
.
clk_200m_o
(
clk_gn4124
)
,
.
rst_200m_n_o
(
rst_gn4124_n
)
,
.
clk_200m_o
(
clk_gn4124
)
,
.
rst_200m_n_o
(
rst_gn4124_n
)
,
.
p2l_clk_p_i
(
i_gn4124
.
p2l_clk_p
)
,
.
p2l_clk_n_i
(
i_gn4124
.
p2l_clk_n
)
,
.
p2l_data_i
(
i_gn4124
.
p2l_data
)
,
...
...
@@ -114,16 +114,17 @@ module main;
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_gn4124;
assign wb_dma_rst_n = rst_gn4124_n;
-----/\----- EXCLUDED -----/\----- */
assign
wb_dma_clk
=
clk_125m
;
assign
wb_dma_rst_n
=
rst_125m_n
;
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_62m5;
assign wb_dma_rst_n = rst_62m5_n;
-----/\----- EXCLUDED -----/\----- */
xwb_dpram
#
(
.
g_size
(
32
)
,
.
g_init_file
(
"mem_init.bram"
)
,
.
g_size
(
16384
)
,
.
g_slave1_interface_mode
(
1
)
,
// 1 = PIPELINED
.
g_slave2_interface_mode
(
1
)
,
.
g_slave1_granularity
(
1
)
,
// 1 = WORD
...
...
@@ -179,7 +180,7 @@ module main;
initial
begin
automatic
int
ntest
=
1
;
const
int
tests
=
9
;
const
int
tests
=
11
;
uint32_t
addr
,
val
,
expected
;
...
...
@@ -191,6 +192,7 @@ module main;
@
(
posedge
clk_125m
)
;
// ---------------------------------
$
write
(
"Test %0d/%0d: simple read/write accesses over Wishbone: "
,
ntest
++,
tests
)
;
...
...
@@ -209,9 +211,11 @@ module main;
acc
.
write
(
addr
,
'h0
)
;
end
repeat
(
2
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
/* -----\/----- EXCLUDED -----\/
-----
// ----------------------------
-----
$
write
(
"Test %0d/%0d: 128B read over DMA, abort after first read: "
,
ntest
++,
tests
)
;
...
...
@@ -221,15 +225,8 @@ module main;
acc
.
write
(
'h14
,
'h80
)
;
// count
acc
.
write
(
'h00
,
'h01
)
;
// start
// Check values read from memory
@(posedge i_gn4124.l2p_valid); // skip header
repeat(2) @(posedge i_gn4124.l2p_clk_p);
expected = 32'h8000001f;
val = i_gn4124.l2p_data;
@(posedge i_gn4124.l2p_clk_n);
val |= i_gn4124.l2p_data << 16;
val_check("DMA read-back", 'h20, val, expected);
// wait for transfer to start
@
(
posedge
i_gn4124
.
l2p_valid
)
;
repeat
(
2
)
@
(
posedge
clk_125m
)
;
...
...
@@ -241,14 +238,42 @@ module main;
repeat
(
2
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
-----/\----- EXCLUDED -----/\----- */
$
write
(
"Test %0d/%0d: 2x128B chained reads over DMA: "
,
// ---------------------------------
$
write
(
"Test %0d/%0d: 256B DMA write: "
,
ntest
++,
tests
)
;
// Setup data in BFM memory
for
(
addr
=
'h00
;
addr
<
'h40
;
addr
+=
1
)
i_gn4124
.
host_mem_write
(
4
*
addr
,
32'h80000020
-
addr
)
;
// Setup DMA
acc
.
write
(
'h14
,
'h100
)
;
// count
acc
.
write
(
'h20
,
'h01
)
;
// attrib
acc
.
write
(
'h0c
,
'h20000000
)
;
// hstartL
acc
.
write
(
'h10
,
'h00000000
)
;
// hstartH
acc
.
write
(
'h00
,
'h01
)
;
// start
@
(
posedge
dma_irq
)
;
check_irq_status
;
clear_irq
;
repeat
(
4
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
// wait for WB transfer to finish
#
5u
s
;
// ---------------------------------
$
write
(
"Test %0d/%0d: 2x128B chained DMA reads: "
,
ntest
++,
tests
)
;
// Setup DMA chain info in BFM memory
i_gn4124
.
host_mem_write
(
'h20000
,
'h0000
100
0
)
;
// remote address
i_gn4124
.
host_mem_write
(
'h20004
,
'h20000
10
0
)
;
// hstartL
i_gn4124
.
host_mem_write
(
'h20000
,
'h0000
008
0
)
;
// remote address
i_gn4124
.
host_mem_write
(
'h20004
,
'h20000
08
0
)
;
// hstartL
i_gn4124
.
host_mem_write
(
'h20008
,
'h00000000
)
;
// hstartH
i_gn4124
.
host_mem_write
(
'h2000C
,
'h80
)
;
// count
i_gn4124
.
host_mem_write
(
'h20010
,
'h00
)
;
// nextL
...
...
@@ -271,11 +296,10 @@ module main;
check_irq_status
;
clear_irq
;
for
(
addr
=
'h00
;
addr
<
'h
2
0
;
addr
+=
1
)
for
(
addr
=
'h00
;
addr
<
'h
4
0
;
addr
+=
1
)
begin
expected
=
32'h800000
00
+
'h20
-
(
addr
%
'h20
)
-
1
;
expected
=
32'h800000
20
-
addr
;
mem_check
(
4
*
addr
,
expected
)
;
mem_check
(
'h100
+
4
*
addr
,
expected
)
;
end
repeat
(
4
)
@
(
posedge
clk_125m
)
;
...
...
@@ -283,7 +307,7 @@ module main;
$
write
(
"PASS
\n
"
)
;
// ---------------------------------
$
write
(
"Test %0d/%0d: 256B
read over DMA
: "
,
$
write
(
"Test %0d/%0d: 256B
DMA read
: "
,
ntest
++,
tests
)
;
// Setup DMA
...
...
@@ -301,7 +325,7 @@ module main;
for
(
addr
=
'h00
;
addr
<
'h40
;
addr
+=
1
)
begin
expected
=
32'h800000
00
+
'h20
-
(
addr
%
'h20
)
-
1
;
expected
=
32'h800000
20
-
addr
;
mem_check
(
4
*
addr
,
expected
)
;
end
...
...
@@ -309,16 +333,57 @@ module main;
$
write
(
"PASS
\n
"
)
;
// ---------------------------------
$
write
(
"Test %0d/%0d: 2x4KiB chained DMA write: "
,
ntest
++,
tests
)
;
// Setup data in BFM memory
for
(
addr
=
'h00
;
addr
<
'h800
;
addr
+=
1
)
i_gn4124
.
host_mem_write
(
4
*
addr
,
32'h80000020
-
addr
)
;
// Setup DMA chain info in BFM memory
i_gn4124
.
host_mem_write
(
'h20000
,
'h00001000
)
;
// remote address
i_gn4124
.
host_mem_write
(
'h20004
,
'h20001000
)
;
// hstartL
i_gn4124
.
host_mem_write
(
'h20008
,
'h00000000
)
;
// hstartH
i_gn4124
.
host_mem_write
(
'h2000C
,
'h1000
)
;
// count
i_gn4124
.
host_mem_write
(
'h20010
,
'h00
)
;
// nextL
i_gn4124
.
host_mem_write
(
'h20014
,
'h00
)
;
// nextH
i_gn4124
.
host_mem_write
(
'h20018
,
'h01
)
;
// attrib
// Setup DMA
acc
.
write
(
'h14
,
'h1000
)
;
// count
acc
.
write
(
'h20
,
'h03
)
;
// attrib
acc
.
write
(
'h0c
,
'h20000000
)
;
// hstartL
acc
.
write
(
'h10
,
'h00000000
)
;
// hstartH
// Point to chain info in BFM memory
acc
.
write
(
'h18
,
'h20020000
)
;
// nextL
acc
.
write
(
'h1C
,
'h00000000
)
;
// nextH
acc
.
write
(
'h00
,
'h01
)
;
// start
@
(
posedge
dma_irq
)
;
check_irq_status
;
clear_irq
;
repeat
(
4
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
// wait for WB transfer to finish
#
5u
s
;
// Check all four byte swap settings
// ---------------------------------
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
$
write
(
"Test %0d/%0d:
16KB read over DMA
(byte swap = %0d): "
,
$
write
(
"Test %0d/%0d:
8KiB DMA read
(byte swap = %0d): "
,
ntest
++,
tests
,
i
)
;
// Restart
acc
.
write
(
'h14
,
'h
4
000
)
;
// count
acc
.
write
(
'h14
,
'h
2
000
)
;
// count
acc
.
write
(
'h20
,
'h00
)
;
// attrib
acc
.
write
(
'h0c
,
'h20000000
+
i
*
'h4000
)
;
// hstartL
acc
.
write
(
'h0c
,
'h20000000
)
;
// hstartL
acc
.
write
(
'h10
,
'h00000000
)
;
// hstartH
acc
.
write
(
'h00
,
(
i
<<
2
)
|
'h01
)
;
// start
...
...
@@ -326,16 +391,16 @@ module main;
check_irq_status
;
for
(
addr
=
'h00
;
addr
<
'h
10
00
;
addr
+=
1
)
for
(
addr
=
'h00
;
addr
<
'h
8
00
;
addr
+=
1
)
begin
expected
=
32'h800000
00
+
'h20
-
(
addr
%
'h20
)
-
1
;
expected
=
32'h800000
20
-
addr
;
if
(
i
==
1
)
expected
=
{<<
8
{
expected
}};
else
if
(
i
==
2
)
expected
=
{<<
16
{
expected
}};
else
if
(
i
==
3
)
expected
=
{<<
16
{{<<
8
{
expected
}}}};
mem_check
(
(
i
*
'h4000
)
+
4
*
addr
,
expected
)
;
mem_check
(
4
*
addr
,
expected
)
;
end
clear_irq
;
...
...
@@ -347,26 +412,26 @@ module main;
#
1u
s
;
end
$
write
(
"Test %0d/%0d:
8KB read over DMA
with 32bit host address overflow: "
,
$
write
(
"Test %0d/%0d:
256B DMA read
with 32bit host address overflow: "
,
ntest
++,
tests
)
;
acc
.
write
(
'h14
,
'h
20
00
)
;
// count
acc
.
write
(
'h14
,
'h
1
00
)
;
// count
acc
.
write
(
'h20
,
'h00
)
;
// attrib
acc
.
write
(
'h0c
,
'hfffff
00
0
)
;
// hstartL
acc
.
write
(
'h0c
,
'hfffff
f8
0
)
;
// hstartL
acc
.
write
(
'h10
,
'h00000000
)
;
// hstartH
acc
.
write
(
'h00
,
'h01
)
;
// start
// Transfer will be split internally by L2P DMA master in two requests, the first
// one with a 32-bit adress starting at ffff_f
00
0 and the next one with a 64-bit
// one with a 32-bit adress starting at ffff_f
f8
0 and the next one with a 64-bit
// address starting at 1_0000_0000
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_dframe
)
;
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
sys_clk
)
;
val_check
(
"Host address overflow header"
,
1
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
'h02ff00
0
0
)
;
val_check
(
"Host address overflow header"
,
1
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
'h02ff00
2
0
)
;
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
sys_clk
)
;
val_check
(
"Host address overflow address"
,
1
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
'hfffff
00
0
)
;
val_check
(
"Host address overflow address"
,
1
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
'hfffff
f8
0
)
;
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_dframe
)
;
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
sys_clk
)
;
val_check
(
"Host address overflow header"
,
2
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
'h03ff00
0
0
)
;
val_check
(
"Host address overflow header"
,
2
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
'h03ff00
2
0
)
;
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
sys_clk
)
;
val_check
(
"Host address overflow address high"
,
2
,
DUT
.
cmp_wrapped_gn4124
.
ldm_arb_data
,
1
)
;
@
(
posedge
DUT
.
cmp_wrapped_gn4124
.
sys_clk
)
;
...
...
hdl/sim/example_tb/mem_init.bram
deleted
100644 → 0
View file @
f1e9a982
10000000000000000000000000011111
10000000000000000000000000011110
10000000000000000000000000011101
10000000000000000000000000011100
10000000000000000000000000011011
10000000000000000000000000011010
10000000000000000000000000011001
10000000000000000000000000011000
10000000000000000000000000010111
10000000000000000000000000010110
10000000000000000000000000010101
10000000000000000000000000010100
10000000000000000000000000010011
10000000000000000000000000010010
10000000000000000000000000010001
10000000000000000000000000010000
10000000000000000000000000001111
10000000000000000000000000001110
10000000000000000000000000001101
10000000000000000000000000001100
10000000000000000000000000001011
10000000000000000000000000001010
10000000000000000000000000001001
10000000000000000000000000001000
10000000000000000000000000000111
10000000000000000000000000000110
10000000000000000000000000000101
10000000000000000000000000000100
10000000000000000000000000000011
10000000000000000000000000000010
10000000000000000000000000000001
10000000000000000000000000000000
hdl/sim/example_tb/wave.do
View file @
0284a69b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_dout
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/dma_packet_len
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/clk_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/target_addr_cnt
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/pd_pdm_data_valid_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/pd_pdm_data_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_wr_d
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_din_d
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_full
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/p2l_rdy_o
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_clk_i
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_empty
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_rd
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_dout
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_valid
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_o
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_clk_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_cyc_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_stb_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_we_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_ack_o
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_adr_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_abort_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_error_i
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_done_i
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_irq_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_direction_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_carrier_addr_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_h_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_l_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_len_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {
537831000 ps} 0
}
WaveRestoreCursors {{Cursor 1} {
6339711 ps} 0} {{Cursor 2} {129899342 ps} 1
}
quietly wave cursor active 1
configure wave -namecolwidth
199
configure wave -valuecolwidth
10
0
configure wave -namecolwidth
277
configure wave -valuecolwidth
21
0
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
...
...
@@ -31,4 +72,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {
737045400
ps}
WaveRestoreZoom {0 ps} {
24072512
ps}
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment