Following up on 6c4dca2c, this commit fixes one issue related to resets and performs
further reset and clock-domain crossing (CDC) cleanup.

Important changes include:

1. Make sure that all dual async fifos are reset on both sides. This solves an issue
   with soft resets causing the host PC to hang.

2. Remove c_RST_ACTIVE constant to make the code simpler.

3. Remove reset from many signals (in particular from wide, data signals) that do not
   need to be reset. This helps with meeting timing wrt reset distribution.

4. Remove synchronizers from p2l deserializers, the SERDES outputs are already synced
   to the FPGA clock.