Commit 72adf76d authored by Dimitris Lampridis's avatar Dimitris Lampridis

Add generics to tune the depths of the various async FIFOs

parent 6a6e3589
......@@ -31,10 +31,13 @@ use work.gencores_pkg.all;
use work.genram_pkg.all;
entity l2p_dma_master is
generic (
g_BYTE_SWAP : boolean := false
);
port (
generic (
g_ADDR_FIFO_FULL_SIZE : positive := 1024;
g_ADDR_FIFO_FULL_THRES : positive := 700;
g_DATA_FIFO_FULL_SIZE : positive := 1024;
g_DATA_FIFO_FULL_THRES : positive := 700;
g_BYTE_SWAP : boolean := FALSE);
port (
-- GN4124 core clk and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -86,9 +89,7 @@ architecture behavioral of l2p_dma_master is
-- Constants
---------------------
constant c_L2P_MAX_PAYLOAD : integer := 32;
constant c_ADDR_FIFO_FULL_THRES : integer := 700;
constant c_DATA_FIFO_FULL_THRES : integer := 700;
constant c_TIMEOUT : integer := 2000;
constant c_TIMEOUT : integer := 2000;
---------------------
-- Signals
......@@ -500,12 +501,12 @@ begin
cmp_addr_fifo: generic_async_fifo_dual_rst
generic map (
g_data_width => 32,
g_size => 1024,
g_size => g_ADDR_FIFO_FULL_SIZE,
g_show_ahead => true,
g_with_wr_full => false,
g_with_wr_almost_full => true,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_ADDR_FIFO_FULL_THRES)
g_almost_full_threshold => g_ADDR_FIFO_FULL_THRES)
port map (
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
......@@ -521,12 +522,12 @@ begin
cmp_data_fifo: generic_async_fifo_dual_rst
generic map (
g_data_width => 32,
g_size => 1024,
g_size => g_DATA_FIFO_FULL_SIZE,
g_show_ahead => true,
g_with_wr_full => false,
g_with_wr_almost_full => true,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_DATA_FIFO_FULL_THRES)
g_almost_full_threshold => g_DATA_FIFO_FULL_THRES)
port map (
rst_wr_n_i => wb_fifo_rst_n,
clk_wr_i => l2p_dma_clk_i,
......
......@@ -33,11 +33,11 @@ use work.genram_pkg.all;
entity p2l_dma_master is
generic (
g_FIFO_SIZE : positive := 512;
g_FIFO_FULL_THRES : positive := 500;
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
g_BYTE_SWAP : boolean := FALSE);
port (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
......@@ -124,7 +124,6 @@ architecture behaviour of p2l_dma_master is
-- Allowed c_MAX_READ_REQ_SIZE values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
......@@ -527,7 +526,7 @@ begin
cmp_to_wb_fifo : generic_async_fifo_dual_rst
generic map (
g_data_width => 64,
g_size => 512,
g_size => g_FIFO_SIZE,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
......@@ -540,7 +539,7 @@ begin
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
g_almost_full_threshold => g_FIFO_FULL_THRES)
port map (
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
......
......@@ -37,10 +37,21 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity gn4124_core is
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wishbone clock cycles)
);
port
(
-- Tunable size and threshold for all async FIFOs.
-- If not sure, leave the defaults.
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
-- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT : positive := 100);
port (
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
......@@ -438,11 +449,13 @@ begin
-- Wishbone master
-----------------------------------------------------------------------------
cmp_wbmaster32 : entity work.wbmaster32
generic map(
g_ACK_TIMEOUT => g_ACK_TIMEOUT
)
port map
(
generic map (
g_TO_WB_FIFO_SIZE => g_WBM_TO_WB_FIFO_SIZE,
g_TO_WB_FIFO_FULL_THRES => g_WBM_TO_WB_FIFO_FULL_THRES,
g_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE,
g_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES,
g_ACK_TIMEOUT => g_ACK_TIMEOUT)
port map (
---------------------------------------------------------
-- Clock/Reset
clk_i => sys_clk,
......@@ -571,8 +584,12 @@ begin
-- L2P DMA master
-----------------------------------------------------------------------------
cmp_l2p_dma_master : entity work.l2p_dma_master
port map
(
generic map (
g_ADDR_FIFO_FULL_SIZE => g_L2P_ADDR_FIFO_FULL_SIZE,
g_ADDR_FIFO_FULL_THRES => g_L2P_ADDR_FIFO_FULL_THRES,
g_DATA_FIFO_FULL_SIZE => g_L2P_DATA_FIFO_FULL_SIZE,
g_DATA_FIFO_FULL_THRES => g_L2P_DATA_FIFO_FULL_THRES)
port map (
clk_i => sys_clk,
rst_n_i => sys_rst_n,
......@@ -615,8 +632,10 @@ begin
-- P2L DMA master
-----------------------------------------------------------------------------
cmp_p2l_dma_master : entity work.p2l_dma_master
port map
(
generic map (
g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES)
port map (
clk_i => sys_clk,
rst_n_i => sys_rst_n,
......
......@@ -55,13 +55,23 @@ package gn4124_core_pkg is
component xwb_gn4124_core is
generic (
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_CFG_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_DAT_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_DAT_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_ACK_TIMEOUT : positive := 100);
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_CFG_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_DAT_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_DAT_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_ACK_TIMEOUT : positive := 100);
port (
rst_n_a_i : in std_logic;
status_o : out std_logic_vector(31 downto 0);
......@@ -105,10 +115,18 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component gn4124_core
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wishbone clock cycles)
);
port
(
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
g_ACK_TIMEOUT : positive := 100);
port (
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
......
......@@ -32,14 +32,27 @@ use work.wishbone_pkg.all;
entity xwb_gn4124_core is
generic (
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_CFG_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_DAT_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_DAT_GRANULARITY : t_wishbone_address_granularity := BYTE;
-- Tunable size and threshold for all async FIFOs.
-- If not sure, leave the defaults.
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
-- WB config for three WB interfaces
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_CFG_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_DAT_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DMA_DAT_GRANULARITY : t_wishbone_address_granularity := BYTE;
-- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT : positive := 100);
g_ACK_TIMEOUT : positive := 100);
port (
---------------------------------------------------------
-- Control and status
......@@ -175,7 +188,17 @@ begin
cmp_wrapped_gn4124 : gn4124_core
generic map (
g_ACK_TIMEOUT => g_ACK_TIMEOUT)
g_WBM_TO_WB_FIFO_SIZE => g_WBM_TO_WB_FIFO_SIZE,
g_WBM_TO_WB_FIFO_FULL_THRES => g_WBM_TO_WB_FIFO_FULL_THRES,
g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE,
g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES,
g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_P2L_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES,
g_L2P_ADDR_FIFO_FULL_SIZE => g_L2P_ADDR_FIFO_FULL_SIZE,
g_L2P_ADDR_FIFO_FULL_THRES => g_L2P_ADDR_FIFO_FULL_THRES,
g_L2P_DATA_FIFO_FULL_SIZE => g_L2P_DATA_FIFO_FULL_SIZE,
g_L2P_DATA_FIFO_FULL_THRES => g_L2P_DATA_FIFO_FULL_THRES,
g_ACK_TIMEOUT => g_ACK_TIMEOUT)
port map (
rst_n_a_i => rst_n_a_i,
status_o => status_o,
......
......@@ -33,10 +33,12 @@ use work.genram_pkg.all;
entity wbmaster32 is
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port
(
g_TO_WB_FIFO_SIZE : positive := 128;
g_TO_WB_FIFO_FULL_THRES : positive := 110;
g_FROM_WB_FIFO_SIZE : positive := 128;
g_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_ACK_TIMEOUT : positive := 100); -- Wishbone ACK timeout (in wb_clk cycles)
port (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
......@@ -98,15 +100,6 @@ end wbmaster32;
architecture behaviour of wbmaster32 is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
constant c_TO_WB_FIFO_SIZE : integer := 128;
constant c_TO_WB_FIFO_FULL_THRES : integer := 110;
constant c_FROM_WB_FIFO_SIZE : integer := 128;
constant c_FROM_WB_FIFO_FULL_THRES : integer := 110;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
......@@ -314,7 +307,7 @@ begin
cmp_fifo_to_wb : generic_async_fifo_dual_rst
generic map (
g_data_width => 66,
g_size => c_TO_WB_FIFO_SIZE,
g_size => g_TO_WB_FIFO_SIZE,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
......@@ -327,7 +320,7 @@ begin
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
g_almost_full_threshold => g_TO_WB_FIFO_FULL_THRES)
port map (
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
......@@ -357,7 +350,7 @@ begin
cmp_from_wb_fifo : generic_async_fifo_dual_rst
generic map (
g_data_width => 34,
g_size => c_FROM_WB_FIFO_SIZE,
g_size => g_FROM_WB_FIFO_SIZE,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
......@@ -370,7 +363,7 @@ begin
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_FROM_WB_FIFO_FULL_THRES)
g_almost_full_threshold => g_FROM_WB_FIFO_FULL_THRES)
port map (
rst_wr_n_i => wb_fifo_rst_n,
clk_wr_i => wb_clk_i,
......
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