hdl: major rehaul of resets and cross-clock domain syncrhonization

Important changes include: 1. Clear separation of resets per clock domain (with the exception of the wbgen-generated dma controller registers). 2. Conversion of all processes to use synchronous resets when the reset is synced with the clock of the process. 3. Use of standard synchronizers from general-cores when crossing clock-domains. Due to the change in processes to use sync resets, a lot of code has changed indentation. To this end, it might be useful to perform a case insensitive diff when studying the changes of this commit. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

hdl: major rehaul of resets and cross-clock domain syncrhonization
Important changes include: 1. Clear separation of resets per clock domain (with the exception of the wbgen-generated dma controller registers). 2. Conversion of all processes to use synchronous resets when the reset is synced with the clock of the process. 3. Use of standard synchronizers from general-cores when crossing clock-domains. Due to the change in processes to use sync resets, a lot of code has changed indentation. To this end, it might be useful to perform a case insensitive diff when studying the changes of this commit. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
6c4dca2c · Dimitris Lampridis · f5b49ca3 · 6c4dca2c · 6c4dca2c · 6c4dca2c
Commit 6c4dca2c authored Apr 12, 2019 by Dimitris Lampridis
10 changed files
--- a/hdl/gn4124core/rtl/dma_controller.vhd
+++ b/hdl/gn4124core/rtl/dma_controller.vhd
--- a/hdl/gn4124core/rtl/l2p_arbiter.vhd
+++ b/hdl/gn4124core/rtl/l2p_arbiter.vhd
@@ -110,71 +110,76 @@ begin
  --         : LDM request
  -- Lowest  : PDM request
  -----------------------------------------------------------------------------
-  process (clk_i, rst_n_i)
+  process (clk_i)
  begin
-    if(rst_n_i = c_RST_ACTIVE) then
-      arb_wbm_gnt <= '0';
-      arb_pdm_gnt <= '0';
-      arb_ldm_gnt <= '0';
-    elsif rising_edge(clk_i) then
-      --if (arb_req_valid = '1') then
-      if (wbm_arb_req_valid = '1') then
-        arb_wbm_gnt <= '1';
-        arb_pdm_gnt <= '0';
-        arb_ldm_gnt <= '0';
-      elsif (ldm_arb_req_valid = '1') then
-        arb_wbm_gnt <= '0';
-        arb_pdm_gnt <= '0';
-        arb_ldm_gnt <= '1';
-      elsif (pdm_arb_req_valid = '1') then
-        arb_wbm_gnt <= '0';
-        arb_pdm_gnt <= '1';
-        arb_ldm_gnt <= '0';
-      elsif (eop = '1') then
+    if rising_edge(clk_i) then
+      if(rst_n_i = c_RST_ACTIVE) then
        arb_wbm_gnt <= '0';
        arb_pdm_gnt <= '0';
        arb_ldm_gnt <= '0';
+      else
+        if (wbm_arb_req_valid = '1') then
+          arb_wbm_gnt <= '1';
+          arb_pdm_gnt <= '0';
+          arb_ldm_gnt <= '0';
+        elsif (ldm_arb_req_valid = '1') then
+          arb_wbm_gnt <= '0';
+          arb_pdm_gnt <= '0';
+          arb_ldm_gnt <= '1';
+        elsif (pdm_arb_req_valid = '1') then
+          arb_wbm_gnt <= '0';
+          arb_pdm_gnt <= '1';
+          arb_ldm_gnt <= '0';
+        elsif (eop = '1') then
+          arb_wbm_gnt <= '0';
+          arb_pdm_gnt <= '0';
+          arb_ldm_gnt <= '0';
+        end if;
      end if;
    end if;
  end process;

-  process (clk_i, rst_n_i)
+  process (clk_i)
  begin
-    if rst_n_i = '0' then
-      arb_ser_valid_t  <= '0';
-      arb_ser_dframe_t <= '0';
-      arb_ser_data_t   <= (others => '0');
-    elsif rising_edge(clk_i) then
-      if arb_wbm_gnt = '1' then
-        arb_ser_valid_t  <= wbm_arb_valid_i;
-        arb_ser_dframe_t <= wbm_arb_dframe_i;
-        arb_ser_data_t   <= wbm_arb_data_i;
-      elsif arb_pdm_gnt = '1' then
-        arb_ser_valid_t  <= pdm_arb_valid_i;
-        arb_ser_dframe_t <= pdm_arb_dframe_i;
-        arb_ser_data_t   <= pdm_arb_data_i;
-      elsif arb_ldm_gnt = '1' then
-        arb_ser_valid_t  <= ldm_arb_valid_i;
-        arb_ser_dframe_t <= ldm_arb_dframe_i;
-        arb_ser_data_t   <= ldm_arb_data_i;
-      else
+    if rising_edge(clk_i) then
+      if rst_n_i = c_RST_ACTIVE then
        arb_ser_valid_t  <= '0';
        arb_ser_dframe_t <= '0';
        arb_ser_data_t   <= (others => '0');
+      else
+        if arb_wbm_gnt = '1' then
+          arb_ser_valid_t  <= wbm_arb_valid_i;
+          arb_ser_dframe_t <= wbm_arb_dframe_i;
+          arb_ser_data_t   <= wbm_arb_data_i;
+        elsif arb_pdm_gnt = '1' then
+          arb_ser_valid_t  <= pdm_arb_valid_i;
+          arb_ser_dframe_t <= pdm_arb_dframe_i;
+          arb_ser_data_t   <= pdm_arb_data_i;
+        elsif arb_ldm_gnt = '1' then
+          arb_ser_valid_t  <= ldm_arb_valid_i;
+          arb_ser_dframe_t <= ldm_arb_dframe_i;
+          arb_ser_data_t   <= ldm_arb_data_i;
+        else
+          arb_ser_valid_t  <= '0';
+          arb_ser_dframe_t <= '0';
+          arb_ser_data_t   <= (others => '0');
+        end if;
      end if;
    end if;
  end process;

-  process (clk_i, rst_n_i)
+  process (clk_i)
  begin
-    if rst_n_i = '0' then
-      arb_ser_valid_o  <= '0';
-      arb_ser_dframe_o <= '0';
-      arb_ser_data_o   <= (others => '0');
-    elsif rising_edge(clk_i) then
-      arb_ser_valid_o  <= arb_ser_valid_t;
-      arb_ser_dframe_o <= arb_ser_dframe_t;
-      arb_ser_data_o   <= arb_ser_data_t;
+    if rising_edge(clk_i) then
+      if rst_n_i = c_RST_ACTIVE then
+        arb_ser_valid_o  <= '0';
+        arb_ser_dframe_o <= '0';
+        arb_ser_data_o   <= (others => '0');
+      else
+        arb_ser_valid_o  <= arb_ser_valid_t;
+        arb_ser_dframe_o <= arb_ser_dframe_t;
+        arb_ser_data_o   <= arb_ser_data_t;
+      end if;
    end if;
  end process;


--- a/hdl/gn4124core/rtl/l2p_dma_master.vhd
+++ b/hdl/gn4124core/rtl/l2p_dma_master.vhd
--- a/hdl/gn4124core/rtl/p2l_decode32.vhd
+++ b/hdl/gn4124core/rtl/p2l_decode32.vhd
--- a/hdl/gn4124core/rtl/p2l_dma_master.vhd
+++ b/hdl/gn4124core/rtl/p2l_dma_master.vhd
--- a/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
--- a/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
--- a/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
+++ b/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
@@ -132,12 +132,14 @@ begin
  ------------------------------------------------------------------------------
  -- data input bit slip
  ------------------------------------------------------------------------------
-  p_din_bitslip : process (sys_clk_i, rst_n_i)
+  p_din_bitslip : process (sys_clk_i)
  begin
-    if rst_n_i = c_RST_ACTIVE then
-      p2l_data_bitslip <= (others => '0');
-    elsif rising_edge(sys_clk_i) then
-      p2l_data_bitslip <= p2l_data_bitslip(0) & '1';
+    if rising_edge(sys_clk_i) then
+      if rst_n_i = c_RST_ACTIVE then
+        p2l_data_bitslip <= (others => '0');
+      else
+        p2l_data_bitslip <= p2l_data_bitslip(0) & '1';
+      end if;
    end if;
  end process p_din_bitslip;

@@ -210,22 +212,24 @@ begin
  p2l_valid_v(0) <= p2l_valid_i;


-  p_in_sys_sync : process (sys_clk_i, rst_n_i)
+  p_in_sys_sync : process (sys_clk_i)
  begin
-    if rst_n_i = c_RST_ACTIVE then
-      p2l_data_o    <= (others => '0');
-      p2l_dframe_o  <= '0';
-      p2l_valid_o   <= '0';
-      p2l_data_t2   <= (others => '0');
-      p2l_dframe_t2 <= '0';
-      p2l_valid_t2  <= '0';
-    elsif rising_edge(sys_clk_i) then
-      p2l_data_t2   <= p2l_data_t;
-      p2l_dframe_t2 <= p2l_dframe_t(0);
-      p2l_valid_t2  <= p2l_valid_t(0);
-      p2l_data_o    <= p2l_data_t2;
-      p2l_dframe_o  <= p2l_dframe_t2;
-      p2l_valid_o   <= p2l_valid_t2;
+    if rising_edge(sys_clk_i) then
+      if rst_n_i = c_RST_ACTIVE then
+        p2l_data_o    <= (others => '0');
+        p2l_dframe_o  <= '0';
+        p2l_valid_o   <= '0';
+        p2l_data_t2   <= (others => '0');
+        p2l_dframe_t2 <= '0';
+        p2l_valid_t2  <= '0';
+      else
+        p2l_data_t2   <= p2l_data_t;
+        p2l_dframe_t2 <= p2l_dframe_t(0);
+        p2l_valid_t2  <= p2l_valid_t(0);
+        p2l_data_o    <= p2l_data_t2;
+        p2l_dframe_o  <= p2l_dframe_t2;
+        p2l_valid_o   <= p2l_valid_t2;
+      end if;
    end if;
  end process p_in_sys_sync;


--- a/hdl/gn4124core/rtl/spartan6/xwb_gn4124_core.vhd
+++ b/hdl/gn4124core/rtl/spartan6/xwb_gn4124_core.vhd
@@ -202,6 +202,7 @@ begin
      dma_irq_o       => dma_irq_o,
      irq_p_i         => irq_p_i,
      irq_p_o         => irq_p_o,
+      dma_reg_rst_n_i => wb_dma_cfg_rst_n_i,
      dma_reg_clk_i   => wb_dma_cfg_clk_i,
      dma_reg_adr_i   => wb_dma_cfg_in.adr,
      dma_reg_dat_i   => wb_dma_cfg_in.dat,
@@ -212,6 +213,7 @@ begin
      dma_reg_dat_o   => wb_dma_cfg_out.dat,
      dma_reg_ack_o   => wb_dma_cfg_out.ack,
      dma_reg_stall_o => wb_dma_cfg_out.stall,
+      csr_rst_n_i     => wb_master_rst_n_i,
      csr_clk_i       => wb_master_clk_i,
      csr_adr_o       => wb_master_out.adr,
      csr_dat_o       => wb_master_out.dat,
@@ -224,6 +226,7 @@ begin
      csr_stall_i     => wb_master_in.stall,
      csr_err_i       => wb_master_in.err,
      csr_rty_i       => wb_master_in.rty,
+      dma_rst_n_i     => wb_dma_dat_rst_n_i,
      dma_clk_i       => wb_dma_dat_clk_i,
      dma_adr_o       => wb_dma_dat_out.adr,
      dma_dat_o       => wb_dma_dat_out.dat,

--- a/hdl/gn4124core/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/rtl/wbmaster32.vhd