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Gennum GN4124 core
Commit 98a2e699 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] simplify DMA WB signal multiplexer

parent 54b5ebf2
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Showing with 59 additions and 66 deletions
hdl/rtl/dma_controller.vhd
View file @ 98a2e699
......@@ -37,6 +37,10 @@ entity dma_controller is
-- Interrupt request
dma_ctrl_irq_o : out std_logic;
---------------------------------------------------------
-- Used to control the DMA WB mux
dma_ctrl_direction_o : out std_logic;
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
......@@ -253,6 +257,7 @@ begin
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_ctrl_direction_o <= '0';
dma_ctrl_abort_o <= '0';
dma_stat_reg <= c_DMA_STAT_IDLE;
......@@ -308,6 +313,7 @@ begin
else
-- P2L transfer (from PCIe to target)
dma_ctrl_start_p2l_o <= '1';
dma_ctrl_direction_o <= '1';
end if;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_stat_reg <= c_DMA_STAT_BUSY;
......
hdl/rtl/l2p_dma_master.vhd
View file @ 98a2e699
......@@ -78,9 +78,7 @@ entity l2p_dma_master is
l2p_dma_stb_o : out std_logic;
l2p_dma_we_o : out std_logic;
l2p_dma_ack_i : in std_logic;
l2p_dma_stall_i : in std_logic;
p2l_dma_cyc_i : in std_logic -- P2L dma WB cycle for bus arbitration
);
l2p_dma_stall_i : in std_logic);
end l2p_dma_master;
architecture behavioral of l2p_dma_master is
......@@ -416,7 +414,7 @@ begin
l2p_dma_dat_o <= (others => '0');
l2p_dma_we_o <= '0';
addr_fifo_valid <= not(addr_fifo_empty or l2p_dma_stall_i or data_fifo_full or p2l_dma_cyc_i);
addr_fifo_valid <= not(addr_fifo_empty or l2p_dma_stall_i or data_fifo_full);
l2p_dma_adr_t <= addr_fifo_dout;
l2p_dma_stb_t <= addr_fifo_rd and not addr_fifo_empty;
......
hdl/rtl/p2l_dma_master.vhd
View file @ 98a2e699
......@@ -98,7 +98,6 @@ entity p2l_dma_master is
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
......@@ -575,8 +574,7 @@ begin
-- fifo read
to_wb_fifo_rd <= not(to_wb_fifo_empty)
and not(p2l_dma_stall_i)
and not(l2p_dma_cyc_i);
and not(p2l_dma_stall_i);
-- write only
p2l_dma_we_o <= '1';
......
hdl/rtl/spartan6/gn4124_core.vhd
View file @ 98a2e699
......@@ -255,6 +255,7 @@ architecture rtl of gn4124_core is
signal dma_ctrl_start_l2p : std_logic;
signal dma_ctrl_start_p2l : std_logic;
signal dma_ctrl_start_next : std_logic;
signal dma_ctrl_direction : std_logic;
signal dma_ctrl_done : std_logic;
signal dma_ctrl_error : std_logic;
......@@ -284,26 +285,23 @@ architecture rtl of gn4124_core is
------------------------------------------------------------------------------
-- DMA wishbone bus
------------------------------------------------------------------------------
signal l2p_dma_adr : std_logic_vector(31 downto 0);
signal l2p_dma_dat_s2m : std_logic_vector(31 downto 0);
signal l2p_dma_dat_m2s : std_logic_vector(31 downto 0);
signal l2p_dma_sel : std_logic_vector(3 downto 0);
signal l2p_dma_cyc : std_logic;
signal l2p_dma_stb : std_logic;
signal l2p_dma_we : std_logic;
signal l2p_dma_ack : std_logic;
signal l2p_dma_stall : std_logic;
signal p2l_dma_adr : std_logic_vector(31 downto 0);
signal p2l_dma_dat_s2m : std_logic_vector(31 downto 0);
signal p2l_dma_dat_m2s : std_logic_vector(31 downto 0);
signal p2l_dma_sel : std_logic_vector(3 downto 0);
signal p2l_dma_cyc : std_logic;
signal p2l_dma_stb : std_logic;
signal p2l_dma_we : std_logic;
signal p2l_dma_ack : std_logic;
signal p2l_dma_stall : std_logic;
signal l2p_dma_adr : std_logic_vector(31 downto 0);
signal l2p_dma_dat : std_logic_vector(31 downto 0);
signal l2p_dma_sel : std_logic_vector(3 downto 0);
signal l2p_dma_cyc : std_logic;
signal l2p_dma_stb : std_logic;
signal l2p_dma_we : std_logic;
signal l2p_dma_ack : std_logic;
signal l2p_dma_stall : std_logic;
signal p2l_dma_adr : std_logic_vector(31 downto 0);
signal p2l_dma_dat : std_logic_vector(31 downto 0);
signal p2l_dma_sel : std_logic_vector(3 downto 0);
signal p2l_dma_cyc : std_logic;
signal p2l_dma_stb : std_logic;
signal p2l_dma_we : std_logic;
signal p2l_dma_ack : std_logic;
signal p2l_dma_stall : std_logic;
--==============================================================================
-- Architecture begin (gn4124_core)
......@@ -529,6 +527,8 @@ begin
dma_ctrl_irq_o => dma_irq,
dma_ctrl_direction_o => dma_ctrl_direction,
dma_ctrl_carrier_addr_o => dma_ctrl_carrier_addr,
dma_ctrl_host_addr_h_o => dma_ctrl_host_addr_h,
dma_ctrl_host_addr_l_o => dma_ctrl_host_addr_l,
......@@ -616,16 +616,14 @@ begin
l2p_dma_rst_n_i => dma_rst_n_i,
l2p_dma_clk_i => dma_clk_i,
l2p_dma_adr_o => l2p_dma_adr,
l2p_dma_dat_i => l2p_dma_dat_s2m,
l2p_dma_dat_o => l2p_dma_dat_m2s,
l2p_dma_dat_i => dma_dat_i,
l2p_dma_dat_o => l2p_dma_dat,
l2p_dma_sel_o => l2p_dma_sel,
l2p_dma_cyc_o => l2p_dma_cyc,
l2p_dma_stb_o => l2p_dma_stb,
l2p_dma_we_o => l2p_dma_we,
l2p_dma_ack_i => l2p_dma_ack,
l2p_dma_stall_i => l2p_dma_stall,
p2l_dma_cyc_i => p2l_dma_cyc
);
l2p_dma_stall_i => l2p_dma_stall);
-----------------------------------------------------------------------------
-- P2L DMA master
......@@ -673,15 +671,14 @@ begin
p2l_dma_rst_n_i => dma_rst_n_i,
p2l_dma_clk_i => dma_clk_i,
p2l_dma_adr_o => p2l_dma_adr,
p2l_dma_dat_i => p2l_dma_dat_s2m,
p2l_dma_dat_o => p2l_dma_dat_m2s,
p2l_dma_dat_i => dma_dat_i,
p2l_dma_dat_o => p2l_dma_dat,
p2l_dma_sel_o => p2l_dma_sel,
p2l_dma_cyc_o => p2l_dma_cyc,
p2l_dma_stb_o => p2l_dma_stb,
p2l_dma_we_o => p2l_dma_we,
p2l_dma_ack_i => p2l_dma_ack,
p2l_dma_stall_i => p2l_dma_stall,
l2p_dma_cyc_i => l2p_dma_cyc,
next_item_carrier_addr_o => next_item_carrier_addr,
next_item_host_addr_h_o => next_item_host_addr_h,
......@@ -693,42 +690,36 @@ begin
next_item_valid_o => next_item_valid
);
p_dma_wb_mux : process (l2p_dma_adr, l2p_dma_cyc, l2p_dma_dat_m2s,
l2p_dma_sel, l2p_dma_stb, l2p_dma_we, p2l_dma_adr,
p2l_dma_cyc, p2l_dma_dat_m2s, p2l_dma_sel,
p2l_dma_stb, p2l_dma_we)
p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i,
l2p_dma_adr, l2p_dma_cyc, l2p_dma_dat, l2p_dma_sel,
l2p_dma_stb, l2p_dma_we, p2l_dma_adr, p2l_dma_cyc,
p2l_dma_dat, p2l_dma_sel, p2l_dma_stb, p2l_dma_we)
begin
if (l2p_dma_cyc = '1') then
dma_adr_o <= l2p_dma_adr;
dma_dat_o <= l2p_dma_dat_m2s;
dma_sel_o <= l2p_dma_sel;
dma_cyc_o <= l2p_dma_cyc;
dma_stb_o <= l2p_dma_stb;
dma_we_o <= l2p_dma_we;
elsif (p2l_dma_cyc = '1') then
dma_adr_o <= p2l_dma_adr;
dma_dat_o <= p2l_dma_dat_m2s;
dma_sel_o <= p2l_dma_sel;
dma_cyc_o <= p2l_dma_cyc;
dma_stb_o <= p2l_dma_stb;
dma_we_o <= p2l_dma_we;
if (dma_ctrl_direction = '0') then
dma_adr_o <= l2p_dma_adr;
dma_dat_o <= l2p_dma_dat;
dma_sel_o <= l2p_dma_sel;
dma_cyc_o <= l2p_dma_cyc;
dma_stb_o <= l2p_dma_stb;
dma_we_o <= l2p_dma_we;
l2p_dma_ack <= dma_ack_i;
l2p_dma_stall <= dma_stall_i;
p2l_dma_ack <= '0';
p2l_dma_stall <= '0';
else
dma_adr_o <= (others => '0');
dma_dat_o <= (others => '0');
dma_sel_o <= (others => '0');
dma_cyc_o <= '0';
dma_stb_o <= '0';
dma_we_o <= '0';
dma_adr_o <= p2l_dma_adr;
dma_dat_o <= p2l_dma_dat;
dma_sel_o <= p2l_dma_sel;
dma_cyc_o <= p2l_dma_cyc;
dma_stb_o <= p2l_dma_stb;
dma_we_o <= p2l_dma_we;
p2l_dma_ack <= dma_ack_i;
p2l_dma_stall <= dma_stall_i;
l2p_dma_ack <= '0';
l2p_dma_stall <= '0';
end if;
end process p_dma_wb_mux;
l2p_dma_dat_s2m <= dma_dat_i;
p2l_dma_dat_s2m <= dma_dat_i;
l2p_dma_ack <= dma_ack_i;
p2l_dma_ack <= dma_ack_i;
l2p_dma_stall <= dma_stall_i;
p2l_dma_stall <= dma_stall_i;
end generate gen_with_dma;
gen_without_dma : if not g_WITH_DMA generate
......
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