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Gennum GN4124 core
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Gennum GN4124 core
Commits
542aa7ea
Commit
542aa7ea
authored
Aug 30, 2019
by
Tristan Gingold
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example_tb: add a simpler multi access DMA transfer.
parent
c211ed08
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1 changed file
with
53 additions
and
23 deletions
+53
-23
main.sv
hdl/sim/example_tb/main.sv
+53
-23
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hdl/sim/example_tb/main.sv
View file @
542aa7ea
...
...
@@ -136,10 +136,24 @@ module main;
val_check
(
"Memory read-back"
,
addr
,
val
,
expected
)
;
endtask
// reg_check
task
check_irq_status
;
// Check irq status
reg_check
(
'h04
,
'h04
)
;
if
(
dma_irq
!=
1'b1
)
$
fatal
(
1
,
"dma irq should be 1"
)
;
endtask
task
clear_irq
;
acc
.
write
(
'h04
,
'h04
)
;
reg_check
(
'h04
,
'h00
)
;
if
(
dma_irq
!=
1'b0
)
$
fatal
(
1
,
"dma irq should be 0"
)
;
endtask
initial
begin
automatic
int
ntest
=
1
;
const
int
tests
=
6
;
const
int
tests
=
7
;
uint32_t
addr
,
val
,
expected
;
...
...
@@ -226,10 +240,7 @@ module main;
@
(
posedge
dma_irq
)
;
// Check irq status
reg_check
(
'h04
,
'h04
)
;
if
(
dma_irq
!=
1'b1
)
$
fatal
(
1
,
"dma irq should be 1"
)
;
check_irq_status
;
for
(
addr
=
'h00
;
addr
<
'h20
;
addr
+=
1
)
begin
...
...
@@ -238,23 +249,48 @@ module main;
mem_check
(
'h100
+
4
*
addr
,
expected
)
;
end
// clear irq
acc
.
write
(
'h04
,
'h04
)
;
reg_check
(
'h04
,
'h00
)
;
if
(
dma_irq
!=
1'b0
)
$
fatal
(
1
,
"dma irq should be 0"
)
;
clear_irq
;
repeat
(
4
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
// ---------------------------------
$
write
(
"Test %0d/%0d: 128 reads over DMA: "
,
ntest
++,
tests
)
;
// Setup DMA
acc
.
write
(
'h14
,
'h100
)
;
// count
acc
.
write
(
'h20
,
'h00
)
;
// attrib
acc
.
write
(
'h0c
,
'h20000000
)
;
// hstartL
acc
.
write
(
'h10
,
'h00000000
)
;
// hstartH
acc
.
write
(
'h00
,
'h01
)
;
// start
@
(
posedge
dma_irq
)
;
check_irq_status
;
for
(
addr
=
'h00
;
addr
<
'h40
;
addr
+=
1
)
begin
expected
=
32'h80000000
+
'h20
-
addr
-
1
;
mem_check
(
4
*
addr
,
expected
)
;
end
clear_irq
;
repeat
(
4
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
// Check all four byte swap settings
// ---------------------------------
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
$
write
(
"Test %0d/%0d:
32
reads over DMA (byte swap = %0d): "
,
$
write
(
"Test %0d/%0d:
16KB
reads over DMA (byte swap = %0d): "
,
ntest
++,
tests
,
i
)
;
// Restart
acc
.
write
(
'h14
,
'h
1
000
)
;
// count
acc
.
write
(
'h14
,
'h
4
000
)
;
// count
acc
.
write
(
'h20
,
'h00
)
;
// attrib
acc
.
write
(
'h0c
,
'h20000000
+
i
*
'h1000
)
;
// hstartL
acc
.
write
(
'h10
,
'h00000000
)
;
// hstartH
...
...
@@ -262,32 +298,26 @@ module main;
@
(
posedge
dma_irq
)
;
// Check irq status
reg_check
(
'h04
,
'h04
)
;
if
(
dma_irq
!=
1'b1
)
$
fatal
(
1
,
"dma irq should be 1"
)
;
check_irq_status
;
for
(
addr
=
'h00
;
addr
<
'h
4
00
;
addr
+=
1
)
for
(
addr
=
'h00
;
addr
<
'h
10
00
;
addr
+=
1
)
begin
expected
=
32'h80000000
+
'h20
-
(
addr
%
'h20
)
-
1
;
$
write
(
"ex: %x"
,
expected
)
;
if
(
i
==
1
)
expected
=
{<<
8
{
expected
}};
else
if
(
i
==
2
)
expected
=
{<<
16
{
expected
}};
else
if
(
i
==
3
)
expected
=
{<<
16
{{<<
8
{
expected
}}}};
$
display
(
"ex: %x"
,
expected
)
;
mem_check
((
i
*
'h1000
)
+
4
*
addr
,
expected
)
;
end
// clear irq
acc
.
write
(
'h04
,
'h04
)
;
reg_check
(
'h04
,
'h00
)
;
if
(
dma_irq
!=
1'b0
)
$
fatal
(
1
,
"dma irq should be 0"
)
;
clear_irq
;
repeat
(
4
)
@
(
posedge
clk_125m
)
;
$
write
(
"PASS
\n
"
)
;
#
1u
s
;
...
...
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