Commits · e0a8b22ce7acb03eb3db68ac97135a5316f99d11 · Projects / FMC DEL 1ns 2cha

07 Sep, 2016 1 commit
- SW: fixed OneWire code; convert to OOP; divided into more files; simplified interface · e0a8b22c
  Jan Pospisil authored Sep 07, 2016
  
  e0a8b22c
05 Sep, 2016 5 commits
- making code OOP - work in progress; DS18B20 temperature readout is working; few bugxifes, typos · be747a84
  Jan Pospisil authored Sep 05, 2016
  
  be747a84
- new version 1.2 · b5c9cb6a
  Jan Pospisil authored Sep 05, 2016
  
  b5c9cb6a
- added version check · a4b0a591
  Jan Pospisil authored Sep 05, 2016
  
  a4b0a591
- Independent Trigger Latency for the two channels (http://www.ohwr.org/issues/1389 ) · 03050f07
  Jan Pospisil authored Sep 05, 2016
  
  03050f07
- added reset of MC100EP140 bad state; better configuration; better debugging;… · 3cdb7af8
  Jan Pospisil authored Sep 05, 2016
```
added reset of MC100EP140 bad state; better configuration; better debugging; comments; attempt for better trigger latency calibration (not working yet)
Signed-off-by: Michael Betz <Michael.Betz@cern.ch>
```
  3cdb7af8
01 Sep, 2016 3 commits
- added HISTORY.txt · f036c33f
  Jan Pospisil authored Sep 01, 2016
  
  f036c33f
- added option for negative pulses · 96dc00c3
  Jan Pospisil authored Sep 01, 2016
  
  96dc00c3
- added version numbers (major.minor.rev); added clock_stable status bit · 9c53d4f4
  Jan Pospisil authored Sep 01, 2016
  
  9c53d4f4
25 Aug, 2016 1 commit
- added patches used on submodules during developement of v1.0 · 6a062568
  Jan Pospisil authored Aug 25, 2016
  
  6a062568
24 Aug, 2016 2 commits
- added license, headers, comments · 88165e5d
  Jan Pospisil authored Aug 24, 2016
  
  88165e5d
- moved testbench for individual entity to the entity directory · 4706f608
  Jan Pospisil authored Aug 24, 2016
  
  4706f608
23 Aug, 2016 7 commits
- tuned RF clock sense · 3801c470
  Jan Pospisil authored Aug 23, 2016
  
  3801c470
- fixed clock stability detection · 473d43a5
  Jan Pospisil authored Aug 23, 2016
  
  473d43a5
- added RF frequency sense · 6cf80089
  Jan Pospisil authored Aug 23, 2016
  
  6cf80089
- fixed mode change detection · a7f7c929
  Jan Pospisil authored Aug 23, 2016
  
  a7f7c929
- added comment · 5d4e76d9
  Jan Pospisil authored Aug 23, 2016
  
  5d4e76d9
- removed default value from net/wire · 6ede4e8b
  Jan Pospisil authored Aug 23, 2016
  
  6ede4e8b
- fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave… · e40c348a
  Jan Pospisil authored Aug 23, 2016
```
fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave default values (always zeros)
```
  e40c348a
22 Aug, 2016 4 commits
- driver updated · d9708bfe
  Jan Pospisil authored Aug 22, 2016
  
  d9708bfe
- added EdgeDetector architecture for both edges detection; added TODO · a84dd5bc
  Jan Pospisil authored Aug 22, 2016
  
  a84dd5bc
- added automatic start-up AD9512 configuration; implemented full clock selection… · 9faab5c0
  Jan Pospisil authored Aug 22, 2016
```
added automatic start-up AD9512 configuration; implemented full clock selection feature; added clock division ratio selection; removed AD9512 SPI slave; fixed FFPG simulation scripts
```
  9faab5c0
- unified "tabs" with the rest of the project (TAB ~ 4 spaces) · 2900dacb
  Jan Pospisil authored Aug 22, 2016
  
  2900dacb
18 Aug, 2016 9 commits
- non-tabifying · 8f0c84ef
  Jan Pospisil authored Aug 18, 2016
  
  8f0c84ef
- added entity for automatic control of AD9512 divider + testbench · 475932c2
  Jan Pospisil authored Aug 18, 2016
  
  475932c2
- changed position of SPI slave initialization to prevent SS_N line glitch · bb9540eb
  Jan Pospisil authored Aug 18, 2016
  
  bb9540eb
- added reset to LOAD_EXT register in WbSlaveWrapper · 544ee006
  Jan Pospisil authored Aug 18, 2016
  
  544ee006
- timing is OK; triggerLatency=0 works · 5e21ea7c
  Jan Pospisil authored Aug 18, 2016
  
  5e21ea7c
- little bit of calibration · 48ce8a91
  Jan Pospisil authored Aug 18, 2016
  
  48ce8a91
- removed one clock domain in top-level, now everything runs on 62.5 MHz; added… · e938e57a
  Jan Pospisil authored Aug 18, 2016
```
removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation
```
  e938e57a
- added default value for lucid beginning of the simulation · 0d512ced
  Jan Pospisil authored Aug 18, 2016
  
  0d512ced
- make OneWire instances better parametrized · 933011a5
  Jan Pospisil authored Aug 18, 2016
  
  933011a5
17 Aug, 2016 5 commits
- fix AD9512 synchronization - now synchronized by Trigger_i · 4a3aa688
  Jan Pospisil authored Aug 17, 2016
  
  4a3aa688
- added memory output registers; improved timing · 7c6f7f70
  Jan Pospisil authored Aug 17, 2016
  
  7c6f7f70
- added bunch-wise configuration possibility · 689cba91
  Jan Pospisil authored Aug 17, 2016
  
  689cba91
- added missing port assignment · 36aac099
  Jan Pospisil authored Aug 17, 2016
  
  36aac099
- added AD9512 synchronization feature (instead of AD9512 reset) · f1b0308f
  Jan Pospisil authored Aug 17, 2016
  
  f1b0308f
16 Aug, 2016 3 commits
- added OneWire function (not working yet); added calculation for pulse configuration · 548e07d3
  Jan Pospisil authored Aug 16, 2016
  
  548e07d3
- TODOs reorganized, added divider generics to OneWire module · 811d92b0
  Jan Pospisil authored Aug 16, 2016
  
  811d92b0
- magical 8 found? · b5dfdd72
  Jan Pospisil authored Aug 16, 2016
  
  b5dfdd72